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freescale semiconductor data sheet: advance information document number: MPC5606S rev. 1, 10/2008 ? freescale semiconductor, inc., 2008. all rights reserved. preliminary?subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MPC5606S tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm lqfp?144 20 mm x 20 mm lqfp?176 24 mm x 24 mm 32-bit mcu for cluster applicat ions with stepper motor, tft graphic controller and lcd driver the MPC5606S family of devices is designed to enable the development of automotive instrument cluster applications by providing a single-chip solution capable of hosting real-time appl ications and driving a tft display directly using an on-chip color tft display controller. MPC5606S devices incorporate a cost-efficient host proce ssor core compliant with the power architecture? embedded category. the processor is 100% user-mode compatible with the original powerpc user instruction set architecture (uisa) and capitalizes on the available development infr astructure of curren t power architecture tm devices with full support from available software drivers, operating systems and config uration code to assist w ith users' implementations. offering high performance processing at speeds up to 64 mhz, the MPC5606S family is optimized for low power consumption and supports a range of on-chip sram and internal flash memo ries. the 1 mb flash version (MPC5606S) features 160 kb of on-chip graphics sram. refer to table 1 for specific memory and feature sets of the product family members. this document describes the features of the MPC5606S family of microcontrollers and highlights important electrical and physical characteristics of the devices. for functional character istics, refer to the MPC5606S microcontroller reference manual. mpc560xs microcontroller data sheet
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 device comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 MPC5606S features. . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 MPC5606S series blocks . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.3.2 block summary . . . . . . . . . . . . . . . . . . . . . . . . . .7 2 pinout and signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . .9 2.1 144 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . .10 2.2 176 lqfp package pinout . . . . . . . . . . . . . . . . . . . . . .11 2.3 208 mapbga package pinout . . . . . . . . . . . . . . . . . . .11 2.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.4.1 pad configuration during reset phases . . . . . .13 2.4.2 voltage supply pins. . . . . . . . . . . . . . . . . . . . . .13 2.4.3 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4.4 system pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.4.5 nexus pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.4.6 functional ports a, b, c, d, e, f, g, h, i, j, k . .18 2.4.7 signal details. . . . . . . . . . . . . . . . . . . . . . . . . . .36 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .39 3.1.1 recommended operating conditions . . . . . . . .41 3.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .44 3.2.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . .45 3.3 emi (electromagnetic interference) characteristics . . .47 3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.4.1 voltage regulator electrical characteristics . . .47 3.4.2 voltage monitor electrical characteristics. . . . . .48 3.4.3 low voltage domain power consumption. . . . . .49 3.5 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .50 3.6 i/o pad electrical characteristics . . . . . . . . . . . . . . . . .50 3.6.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.6.2 i/o input dc characteristics . . . . . . . . . . . . . . 50 3.6.3 i/o output dc characteristics . . . . . . . . . . . . . 51 3.6.4 i/o pad current specification. . . . . . . . . . . . . . 55 3.7 reset electrical characteristics . . . . . . . . . . . . . . . . . 57 3.8 main oscillator electrical characteristics . . . . . . . . . . 59 3.9 low power oscillator electrical characteristics. . . . . . 61 3.10 fmpll electrical characteristics. . . . . . . . . . . . . . . . . 62 3.11 main rc oscillator electrical characteristics . . . . . . . 63 3.12 low power rc oscillator electrical characteristics . . 64 3.13 flash memory electrical charac teristics . . . . . . . . . . . 64 3.14 analog to digital converter (adc) electrical characteristics 65 3.14.1 input impedance and adc accuracy . . . . . . . . 66 3.14.2 adc electrical characteristics . . . . . . . . . . . . . 70 3.15 ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.15.1 pad ac specifications . . . . . . . . . . . . . . . . . . . 72 3.16 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.16.1 ieee 1149.1 interface timing . . . . . . . . . . . . . 74 3.16.2 nexus debug interface. . . . . . . . . . . . . . . . . . . 77 3.16.3 interface to tft lcd panels . . . . . . . . . . . . . . 78 3.16.4 external interrupt (irq) and non-maskable interrupt (nmi) timing . . . . . . . . . . . . . . . . . . . 81 3.16.5 enhanced modular i/o subsystem (emios) timing 82 3.16.6 flexcan timing . . . . . . . . . . . . . . . . . . . . . . . . 82 3.16.7 deserial serial peripheral interface (dspi) . . . 83 3.16.8 i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.16.9 mechanical outline drawings. . . . . . . . . . . . . . 89 3.17 144 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.18 176 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
overview mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 3 1 overview the following sections provide high-level descri ptions of the features found on the MPC5606S. 1.1 device comparison .. table 1. MPC5606S family feature mpc5602s mpc5604s MPC5606S cpu e200z0h execution speed static - 64 mhz flash (ecc) 256 kb 512 kb 1 mb eeprom emulation block (ecc) 4 16 kb ram (ecc) 24 kb 48 kb 48 kb graphics ram no no 160 kb mpu 12 entry edma 16 channels display control unit no no yes parallel data interface no no yes stepper motor controller 6 motors stepper motor stall detect yes sound generation yes yes using emios lcd segment driver 64 6 64 6 40 4, 38 6 1 32 khz external crystal oscillator ye s real time counter and autonomous periodic interrupt ye s ye s ye s periodic interrupt timer 4 ch, 32-bit system watchdog timer yes system timer module 4 ch, 32-bit timed i/o 2 8 ch, 16-bit ic/oc 16 ch, 16-bit opwm/ic/oc adc 3 16 channels, 10-bit can (64 mailboxes) 1 flexcan 2 flexcan 2 flexcan can sampler yes sci 2 linflex spi 2 dspi 2 dspi 3 4 dspi quadspi serial flash interface no no yes
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice overview freescale semiconductor 4 i 2 c 224 gpio 105 105 105 / 132 debug nexus 1 nexus 1 nexus 2+ 5 package 144 lqfp 144 lqfp 144 lqfp 6 176 lqfp 208 mapbga 7 1 configuration is so ftware-programmable 2 ic-input capture, oc-output compare, opwm-output pulse width modulation 3 support for external multiplexer enabling up to 23 channels 4 quadspi serial flash controller can be optionally used as a third dspi 5 nexus2+ available on 176 lqfp as alte rnate pin function and on 208 mapbga 6 not all features are available simultaneously in 144 lqfp package option 7 the 208-pin package is not a production package; it is available in limited quantities for tool development only. table 1. MPC5606S family (continued) feature mpc5602s mpc5604s MPC5606S
overview mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 5 1.2 MPC5606S features ? single issue, 32-bit power architecture book e compliant cpu core complex (e200z0h) ? compatible with classic powerpc instruction set ? includes variable length encoding (vle) instruction se t for smaller code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction over conventional book e compliant code ? on-chip ecc flash memory with flash controller ? up to 1 mb primary flash?two 51 2 kb modules with prefetch buffer and 128-bit data access port ? 64 kb data flash?separate 4 16 kb flash block for eeprom emulation w ith prefetch buffer and 128-bit data access port ? up to 48 kb on-chip ecc sram with sram controller ? up to 160 kb on-chip non-ecc graphics sram with sram controller ? memory protection unit (mpu) with up to 12 region de scriptors and 32-byte region granularity to provide basic memory access permission ? interrupt controller (intc) with up to 127 periphe ral interrupt sources and eight software interrupts ? two frequency-modulated phase-locked loops (fmplls) ? primary fmpll provides a 64 mhz system clock ? auxiliary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory or ram from multiple bus masters (amba 2.0 v6 ahb) ? 16-channel enhanced direct memory access controller (edma) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) for embedded boot code supports boot options including download of code via a serial link (can or spi) ? display control unit to drive tft lcd displays. it includes pr ocessing of up to four planes that can be blended together and offers a direct un-buffered hardware bit-blitter of up to 16 software-configurable dynamic layers in order to drastically minimize graphic me mory requirements and provide fast anima tions. programmable display resolutions are available up to wvga. ? parallel data interface for digital video input ? the lcd segment driver module has two software programmable configurations: ? up to 40 front plane driv ers and 4 backplane drivers ? up to 38 frontplane driver s and 6 backplane drivers ? stepper motor controller module with high-current drivers fo r up to six instrument cluster gauges driven in full dual h-bridge configuration including full di agnostics for short circuit detection ? stepper motor return-to-zero and stall detection module ? sound generation and playback utilizing pwm channels and edma; supports monotonic and polyphonic sound ? 24 emios channels providing up to 16 pwm and 24 input capture / output compare channels ? 10-bit analog-to-digital converter (adc) with a maximum conversion time of 1 s ? 16 internal channels ? extendable to eight multi plexed external channels ? up to three dspi (deserial serial pe ripheral interface) modules for full-dup lex, synchronous, co mmunications with external devices ? quadspi serial flash memory controll er supporting single, dual and quad mode s of operation to interface to external serial flash memory or optionally can be configured to function as another dspi module (MPC5606S only) ? two local interconnect network (lin) controller module s capable of autonomous message handling (master), autonomous header handling (slave mode), and uart support. compliant with lin protocol rev 2.1
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice overview freescale semiconductor 6 ? two full can 2.0b controllers with 64 configurable buffers each; the bit rate can be programmed up to 1 mb/s ? up to four inter-integrated circuit (i 2 c) internal bus controllers with master/slave bus interface ? up to 132 configurable general purpose pins supporting input and output operations ? real time counter (rtc). clock sources are: ? internal 128 khz or 16 mhz rc oscillator supporting au tonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds ? external 32 khz crystal oscillator, supporting wake-up with 1 s resolution and maximum timeout of one hour ? external 4 - 16 mhz oscillator ? system timers: ? 4-channel 32-bit system timer module (stm)?included in processor platform ? 4-channel 32-bit periodic interrupt timer (pit) module ? system watchdog timer ? system integration unit (siu) module to manage resets, external interrupts, gpio and pad control ? system status and configuration module (sscm) to provide information for identification of the device, last boot mode, or debug status and provides an entry point for the censorship password mechanism ? clock generation module (cgm) to generate system clock sources and provide a unified register interface, enabling access to all clock sources ? clock monitor unit (cmu) to monitor the integrity of the main crystal oscillator and the pll and act as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock ? mode entry module (mem) to control the device power m ode, i.e., run, halt, stop, or standby, control mode transition sequences, and manage the power control, volta ge regulator, clock generation and clock management modules ? reset generation module (rgm) to manage reset asse rtion and release to the device at initial power-up ? nexus development interface (ndi) per i eee-isto 5001-2003 class two plus standard ? device/board boundary-scan testing supported per joint te st action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator controller for regulating the 3.3 or 5 v supply voltage down to 1.2 v for core logic (requires external ballast transistor) ? the MPC5606S microcontrollers are offered in the following packages: 1 ? 144 lqfp, 0.5 mm pitch, 20 mm 20 mm outline ? 176 lqfp, 0.5 mm pitch, 24 mm 24 mm outline ? 208 mapbga, 1.0 mm pitch, 17 mm 17 mm outline 1.3 MPC5606S series blocks 1.3.1 block diagram figure 1 shows a top-level block diagram of the MPC5606S series. 1. see the device comparison table or orderable parts summary for package offerings for each device in the family.
overview mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 7 figure 1. MPC5606S series block diagram 1.3.2 block summary table 2 summarizes the functions of all blocks present in the MPC5606S series microc ontrollers. please note that the presence and number of blocks varies by device and package. six gauge drivers with stepper stall detect (ssd) 16 + 8 ch. 2 dspi test controller nexus 2+ nexus siu reset control interrupt external imux gpio & jtag crossbar switch pad control jtag port nexus port e200z0h external blocks 32-bit controller 2 flexcan 4 x 4 peripheral bridge peripheral interrupts from interrupt request external interrupts i/o instructions data voltage regulator nmi swt stm nmi siu . . . . . . . . . . . . (intc) 4 i 2 c . . . 2 linflex 2 x emios 16 ch. adc mpu (memory protection unit) clock monitor unit (cmu) controller flash flash power control mode entry clock generation module reset generation module unit module bam rtc/ sscm api 10-bit . . . dma dcu rgb tft output parallel data (pdi) interface irc irc xosc xosc xtal/ extal xtal32/ extal32 16 mhz 128 khz 4-16 mhz 32 khz 4pit lcd fp and bp signals sound generation speaker/ buzzer data and clock quadspi controller sram sram 2 fmpll port controller video controller sram sram 40 4 lcd
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice overview freescale semiconductor 8 table 2. MPC5606S series block summary block function 16-channel 2nd-generation direct memory access (edma) second-generation platform module capable of performing complex data transfers with minimal intervention from a host processor via ? n ? programmable channels ahb crossbar switch ?lite? (xbar-lite) internal busmaster analog-to-digital converter (adc) 16-channel, 10-bit analog to digital converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (cgm) provides logic and control required for the generation of system and peripheral clocks clock monitor unit (cmu) monitors clock source (internal and external) integrity display control unit (dcu) generates all signals required to drive a tft lcd display, allowing blending of data of up to 16 layers; can also display digital video/graphics in the background plane deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices quadspi (qspi) provides a synchronous serial bus for communication with external serial flash memory and is optionally configurable as a third dspi module enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modulated phase-locked loop) two fmplls generate high-speed system clocks and support programmable frequency modulation inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority- based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode lcd driver module provides 40 4 (frontpl ane drivers backplane drivers) or 6 38 driver configuration for driving lcd segments linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) p rovides hardware access contro l for all memory references generated in a device error correction status module (ecsm) provides misce llaneous control functions including program-visible information about the platform configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and generic access error information for the processor core
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 9 2 pinout and signal descriptions mode entry module (mem) provides a mechanism for controlling the device operational mode and mode transition sequences in al l functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configurati on, control and status registers accessible for applications nexus development interface (ndi) level provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard peripheral interrupt timer (pit) produces periodic interrupts and triggers power control unit (pcu) reduces the overall po wer consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu static random-access memory (sram) provides stor age for program code, constants, and variables reset generation module (rgm) centralizes reset s ources and manages the device reset sequence of the device real time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a pre-defined interval independent of the mode of operation (run mode or low-power mode) sound generation logic (sgl) provides monotonic and polyphonic sound generation capability stepper motor controller (smc) a pw m motor controller suitable for driving instruments in a cluster configuration or any other loads requiring a pwm signal stepper stall detect (sdd) the ssd module conne cts to one stepper (sm) motor with 2 coils and is used to monitor the movement of the sm to detect that the attached gauge pointer has reached the stall position of the scale system integration unit (siu) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general -purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status configuration module (sscm) provides system configuration and status data, e.g., memory size and status, device mode and security status, dma status, etc., device identification data, deb ug status port enable and selection, and bus and peripheral abort enable/disable system timer (stm) provides a set of output compare events to support autosar and operating system tasks system watchdog timer (swt) provides protection from runaway code test control unit (tcu) an extension of the jtag controller module, the tcu provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode table 2. MPC5606S series block summary (continued) block function
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 10 2.1 144 lqfp package pinout figure 2 shows the pinout for the 144-pin lqfp package. warning any pins labeled ?nc? must not be connected to any external circuit. figure 2. 144-pin lqfppinout 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144-pin lqfp 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/pf2 vdde_b vsse_b pcs_a2/emiosb19/rxd_b/pb12 pcs_a1/emiosb18/txd_b/pb13 vdd12 vss12 emiosb20/sck_a/pb9 emiosb21/sout_a/pb8 emiosb22/sin_a/pb7 clkout/emiosb16/pcs_a0/ph4 ma0/sck_b/pb4 fabm/ma1/sout_b/pb5 abs[0]/ma2/sin_b/pb6 vdd12 vss12 vdda vssa xtal32/an15/pc15 extal32/an14/pc14 pcs_b0/ma2/an13/pc13 pcs_b1/ma1/an12/pc12 pcs_b2/ma0/an11/pc11 sound/an10(mux)/pc10 an9/pc9 an8/pc8 vdde_c vsse_c an7/pc7 an6/pc6 an5/pc5 an4/pc4 an3/pc3 an2/pc2 an1/pc1 an0/pc0 pa9/dcu_g1/emiosb18/sda_c/fp14 pa8/dcu_g0/emiosb23/scl_c/fp15 pa7/dcu_r7/emiosa16/fp16 pa6/dcu_r6/emiosa15/fp17 pa5/dcu_r5/emiosa17/fp18 pa4/dcu_r4/emiosa18/fp19 pa3/dcu_r3/emiosa19/sscm7/fp20 pa2/dcu_r2/emiosa20/sscm6/fp21 pa1/dcu_r1/emiosa21/sscm5/fp22 pa0/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/sck_c/fp24 pf14/sout_c/cntx_b/sscm4/fp25 pf13/sin_c/cnrx_b/sscm3/fp26 pf12/emiosb16/pcs_c2/sscm2/fp27 pf11/emiosb23/pcs_c1/sscm1/fp28 pf10/emiosa16/pcs_c0/sscm0/fp29 pg12/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/scl_b/pcs_b0/txd_b/fp31 pf8/sda_b/pcs_b1/rxd_b/fp32 pf7/scl_a/pcs_b2/fp33 pf6/sda_a/fp34 vss12 vdd12 pf5/emiosa9/dcu_tag/fp35 pf4/emiosa10/pdi7/fp36 pf3/emiosa11/pdi6/fp37 pf1/emiosa12/pdi5/emiosa21/fp38 pf0/emiosa13/pdi4/emiosa22/fp39 pb2/txd_a pb3/rxd_a vsse_e vdde_e pb11/cntx_b/pdi3/emiosa16 pb10/cnrx_b/pdi2/emiosa23 pb0/cntx_a/pdi1 pb1/cnrx_a/pdi0 vss12 vdd12 pe7/m5c1p/ssd5_3/emiosa8 pe6/m5c1m/ssd5_2/emiosa9 pe5/m5c0p/ssd5_1/emiosa10 pe4/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/m4c1p/ssd4_3/emiosa12 pe2/m4c1m/ssd4_2/emiosa13 pe1/m4c0p/ssd4_1/emiosa14 pe0/m4c0m/ssd4_0/emiosa15 pd15/m3c1p/ssd3_3 pd14/m3c1m/ssd3_2 pd13/m3c0p/ssd3_1 pd12/m3c0m/ssd3_0 vssmb vddmb pd11/m2c1p/ssd2_3 pd10/m2c1m/ssd2_2 pd9/m2c0p/ssd2_1 pd8/m2c0m/ssd2_0 pd7/m1c1p/ssd1_3/emiosb16 pd6/m1c1m/ssd1_2/emiosb17 pd5/m1c0p/ssd1_1/emiosb18 pd4/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/m0c1p/ssd0_3/emiosb20 pd2/m0c1m/ssd0_2/emiosb21 pd1/m0c0p/ssd0_1/emiosb22 pd0/m0c0m/ssd0_0/emiosb23 fp13/emiosb20/dcu_g2/pa10 fp12/emiosa13/dcu_g3/pa11 fp11/emiosa12/dcu_g4/pa12 fp10/emiosa11/dcu_g5/pa13 fp9/emiosa10/dcu_g6/pa14 fp8/emiosa9/dcu_g7/pa15 vdde_a vsse_a fp7/sound/scl_d/dcu_b0/pg0 fp6/sda_d/dcu_b1/pg1 fp5/emiosb19/dcu_b2/pg2 fp4/emiosb21/dcu_b3/pg3 fp3/emiosb17/dcu_b4/pg4 fp2/emiosa8/dcu_b5/pg5 fp1/dcu_b6/pg6 fp0/dcu_b7/pg7 bp0/dcu_vsync/pg8 bp1/dcu_hsync/pg9 bp2/dcu_de/pg10 bp3/dcu_pclk/pg11 vlcd/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll nc tdi/ph1 tdo/ph2 tms/ph3 tck/ph0
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 11 2.2 176 lqfp package pinout figure 3 shows the pinout for the 176-pin lqfp package. warning any pins labeled ?nc? must not be connected to any external circuit. figure 3. 176-pin lqfp pinout 2.3 208 mapbga package pinout figure 4 shows the pinout for the 208-pin bga package. 176-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa9/dcu_g1/emiosb18/sda_c/fp14 pa8/dcu_g0/emiosb23/scl_c/fp15 pa7/dcu_r7/emiosa16/fp16 pa6/dcu_r6/emiosa15/fp17 pa5/dcu_r5/emiosa17/fp18 vsse_a vdde_a pa4/dcu_r4/emiosa18/fp19 pa3/dcu_r3/emiosa19/sscm7/fp20 pa2/dcu_r2/emiosa20/sscm6/fp21 pa1/dcu_r1/emiosa21/sscm5/fp22 pa0/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/sck_c/fp24 pf14/sout_c/cntx_b/sscm4/fp25 pf13/sin_c/cnrx_b/sscm3/fp26 pf12/emiosb16/pcs_c2/sscm2/fp27 pf11/emiosb23/pcs_c1/sscm1/fp28 pf10/emiosa16/pcs_c0/sscm0/fp29 pg12/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/scl_b/pcs_b0/txd_b/fp31 pf8/sda_b/pcs_b1/rxd_b/fp32 pf7/scl_a/pcs_b2/fp33 pf6/sda_a/fp34 vss12 vdd12 pf5/emiosa9/dcu_tag/fp35 pf4/emiosa10/pdi7/fp36 pf3/emiosa11/pdi6/fp37 pf1/emiosa12/pdi5/emiosa21/fp38 pf0/emiosa13/pdi4/emiosa22/fp39 pk1/pdi13/emiosa17 pk0/pdi12/emiosa18/dcu_tag pb2/txd_a pb3/rxd_a pj15/pdi11/emiosa19 pj14/pdi10/emiosa20 pj13/pdi9/emiosb20 pj12/pdi8/emiosb17 vsse_e vdde_e nmi/pf2 vdde_b vsse_b pcs_a2/emiosb19/rxd_b/pb12 pcs_a1/emiosb18/txd_b/pb13 vdd12 vss12 emiosa15/sda_b/pk10 emiosa14/scl_b/pk11 emiosb20/sck_a/pb9 emiosb21/sout_a/pb8 emiosb22/sin_a/pb7 cnrx_a/pdi0/pj4 cntx_a/pdi1/pj5 emiosa22/cnrx_b/pdi2/pj6 emiosa21/cntx_b/pdi3/pj7 clkout/emiosb16/pcs_a0/ph4 ma0/sck_b/pb4 fabm/ma1/sout_b/pb5 vdde_b vsse_b abs[0]/ma2/sin_b/pb6 vdd12 vss12 vdda vssa xtal32/an15/pc15 extal32/an14/pc14 pcs_b0/ma2/an13/pc13 pcs_b1/ma1/an12/pc12 pcs_b2/ma0/an11/pc11 sound/an10(mux)/pc10 an9/pc9 an8/pc8 vdde_c vsse_c an7/pc7 an6/pc6 an5/pc5 an4/pc4 an3/pc3 an2/pc2 an1/pc1 an0/pc0 pb11/cntx_b/pdi3/emiosa16 pb10/cnrx_b/pdi2/emiosa23 pb0/cntx_a/pdi1 pb1/cnrx_a/pdi0 pj11/pdi7 pj10/pdi6 pj9/pdi5 pj8/pdi4 vss12 vdd12 pj3/pdi_pclk pj2/pdi_vsync pj1/pdi_hsync pj0/pdi_de pe7/m5c1p/ssd5_3/emiosa8 pe6/m5c1m/ssd5_2/emiosa9 pe5/m5c0p/ssd5_1/emiosa10 pe4/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/m4c1p/ssd4_3/emiosa12 pe2/m4c1m/ssd4_2/emiosa13 pe1/m4c0p/ssd4_1/emiosa14 pe0/m4c0m/ssd4_0/emiosa15 pd15/m3c1p/ssd3_3 pd14/m3c1m/ssd3_2 pd13/m3c0p/ssd3_1 pd12/m3c0m/ssd3_0 vssmb vddmb pd11/m2c1p/ssd2_3 pd10/m2c1m/ssd2_2 pd9/m2c0p/ssd2_1 pd8/m2c0m/ssd2_0 pd7/m1c1p/ssd1_3/emiosb16 pd6/m1c1m/ssd1_2/emiosb17 pd5/m1c0p/ssd1_1/emiosb18 pd4/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/m0c1p/ssd0_3/emiosb20 pd2/m0c1m/ssd0_2/emiosb21 pd1/m0c0p/ssd0_1/emiosb22 pd0/m0c0m/ssd0_0/emiosb23 fp13/emiosb20/dcu_g2/pa10 fp12/emiosa13/dcu_g3/pa11 fp11/emiosa12/dcu_g4/pa12 fp10/emiosa11/dcu_g5/pa13 fp9/emiosa10/dcu_g6/pa14 fp8/emiosa9/dcu_g7/pa15 vdde_a vsse_a fp7/sound/scl_d/dcu_b0/pg0 fp6/sda_d/dcu_b1/pg1 fp5/emiosb19/dcu_b2/pg2 fp4/emiosb21/dcu_b3/pg3 fp3/emiosb17/dcu_b4/pg4 fp2/emiosa8/dcu_b5/pg5 fp1/dcu_b6/pg6 fp0/dcu_b7/pg7 bp0/dcu_vsync/pg8 bp1/dcu_hsync/pg9 bp2/dcu_de/pg10 bp3/dcu_pclk/pg11 vlcd/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll nc pdi10/mcko/pk2 pdi11/mseo/pk3 pdi12/evto/pk4 tdi/ph1 pdi13/evti/pk5 pdi14/mdo0/pk6 tdo/ph2 pdi15/mdo1/pk7 tms/ph3 pdi16/mdo2/pk8 tck/ph0 pdi17/mdo3/pk9
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 12 warning any pins labeled ?nc? must not be connected to any external circuit. figure 4. 208-pin mapbga pinout 2.4 signal description 1 2 3 4 5 6 7 8 9 1011121314 1516 a pa 0 pj0 pj1 pj3 pj5 pj7 pj14 pf0 pf5 pk9 pk5 nc nc pf10 pf11 pf12 b pa 1 v d d e _ a pj2 pj4 pj6 pj8 pj15 pf1 pf6 nc pk6 pk2 nc nc vdde_e pf13 c pa2 pa3 vdde_a pj9 pj10 pj12 pk0 pf3 pf7 nc pk7 pk3 nc vdde_ e nc pf14 d pa 4 pa 5 pg0 vdd12 pj11 pj13 pk1 pf4 vdd12 pg12 pk8 pk4 vdd12 nc nc pf15 e pa 6 pa 7 pg1 pg2 nc nc nc nc f pa 8 pa 9 pg3 pg4 nc nc nc nc g pa 1 0 pa 1 1 pg5 pg6 vss vss vss vss nc pe7 pe1 nc h pa 1 2 pa 1 3 pa 1 5 pg7 vss vss vss vss pe5 pe6 vddmc vssmc j reset pa14 pg8 pg10 vss vss vss vss pe4 pe2 pe0 pd8 k extal vdde_a pg9 pg11 vss vss vss vss pe3 pd13 pd9 pd7 l vsspll vddpll nmi/pf2 mdo3 pd15 pd12 vddmb vssm b m xtal vpp ph3 vreg bypass pd14 pd11 pd5 pd6 n vddr vlcd ph2 vdd12 pk11 pk10 pb8 pb5 pc13 pc9 pc6 pb11 vddma pd10 pd4 pd3 p vrc_ ctrl ph1 vdde_b mdo2 mdo1 pb13 pb7 pb4 pc12 pc8 pc5 pc3 pb10 nc pd2 pd1 r ph0 vdde_b evto pf9 ph4 pb12 pb6 pc15 pc11 pc7 pc4 pc2 pb3 pb2 vdde_b pd0 t mcko mseo evti pf8 mdo0 pb9 vdde_c pc14 pc10 vssa vdda pc1 pc0 pb1 pb0 vssma
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 13 the following sections provide signal descriptions and re lated information about the functionality and configuration. 2.4.1 pad configuratio n during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. after power-up phase, all pads are floating with the following exceptions: ? analog input pins an[0:9] are pull-up ? evti (208-pin package only) is pull-up. ? pb[6] (fab) is pull-up. without external strong pull-up the device starts fetching from flash ? reset pad is driven low. this is released only after phase2 reset completion. ? main oscillator pads (extal, xtal) are tristate. ? pa[0] dcu_r0 is pull-up ? pb[1] cnrx_a is pull-up ? pb[10] cnrx_b is pull-up ? pb[12] rxd_b is pull-up ? pb[3] rxd_a is pull-up ? pb[4] sck_b is pull-up ? pf[0] emiosa13 is pull-up ? pf[11] emiosb23 is pull-up ? pf[13] sin_c is pull-up ? pf[2] nmi is pull-up ? pf[3] emiosa11 is pull-up ? pf[5] emiosa9 is pull-up ? pf[6] sda_a is pull-up ? pf[8] sda_b is pull-up ? ph[0] tck is pull-up ? ph[1] tdi is pull-up ? ph[3] tms is pull-up ? pj[4] pdi0 is pull-up ? pj[6] pdi2 is pull-up ? pk[9] mdo3 is pull-up 2.4.2 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used fo r 1.2 v regulator stabilization.
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 14 table 3. voltage supply pin descriptions supply pin function pin number 144 lqfp 176 lqfp 208 mapbga v dd12 1 1.2 v core supply (1.08 v - 1.32 v) 42, 51, 103, 118, 133 50, 67, 123, 148, 163 d4, d9, d13, n4 v ss12 low voltage ground for core domain 43, 52, 104, 119, 134 51, 68, 124, 149, 164 ? v ss low voltage ground ? ? g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 v dda 3.3 v/5 v reference voltage and analog supply for a/d converter 53 69 t11 v ssa reference ground and analog ground for a/d converter 54 70 t10 v ddr voltage regulator vreg supply 22 22 n1 v ssr voltage regulator ground 23 23 ? v dde_a 3.3 v/5 v i/o supply. this supply is shared with internal flash and 16 mhz irc oscillator. 7, 124 7, 154, 170 b2, c3, k2 v sse_a 3.3 v/5 v i/o supply ground 8, 125 8, 155, 171 ? v dde_b 3.3 v/5 v i/o supply. 4-16 mhz crystal oscillator shares this supply. 38 46, 64 p3, r2, r15 v sse_b 3.3 v/5 v i/o supply ground 39 47, 65 ? v dde_c 3.3 v/5 v i/o supply. 32 khz oscillator shares this supply with adc. 63 79 t7 v sse_c 3.3 v/5 v i/o supply ground 64 80 ? v dde_e 3.3 v/5 v i/o supply 109 133 b15, c14 v sse_e 3.3 v/5 v i/o supply ground 110 134 ? v ddma 2 stepper motor 5 v pad supply. ssd shares this supply. 77 93 n13 v ssma stepper motor ground 78 94 t16 v ddmb 2 stepper motor 5 v pad supply. ssd shares this supply. 87 103 l15 v ssmb stepper motor ground 88 104 l16 v ddmc 2 stepper motor 5 v pad supply. ssd shares this supply. 97 113 h15 v ssmc stepper motor ground 98 114 h16 v ddpll 1.2 v pll supply 31 31 l2
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 15 2.4.3 pad types in the device the following types of pads are avai lable for system pins and functional port pins: s = slow 1 m = medium 1,2 f = fast 1,2 i = input only with analog feature 1 j = input/output with analog feature x = oscillator 2.4.4 system pins the system pins are listed in table 4 . v sspll pll ground 30 30 l1 v ssosc oscillator ground 28 28 ? v lcd 3 lcd supply option 21 21 n2 v pp 4 9 v - 12 v flash test analog write signal 26 26 m2 1 decoupling capacitors must be connected between these pins and the nearest v ss12 pin. 2 all stepper motor supplies need to be at same level (3.3 v or 5 v). 3 refer to lcd segment of reference manual for us age of vlcd as supply/reference voltage source. 4 this signal needs to be connected to ground during normal operation. 1. refer to section 3.6, ?i/o pad electrical characteristics , for details 2. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (refer to pcr.src in the device reference manual, pa d configuration registers (pcr0 - pcr120)). table 3. voltage supply pin descriptions (continued) supply pin function pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 16 2.4.5 nexus pins table 4. system pin descriptions system pin function i/o direction pad type reset configuration pin number 144 lqfp 176 lqfp 208 mapbga reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull up 24 24 j1 extal analog output of the oscillator amplifier circuit. input for the clock generator in bypass mode. ox ? 29 29 k1 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ix ? 27 27 m1 extal32 analog input of the 32khz oscillator amplifier circuit. o ? 56 72 ? xtal32 analog output of the 32 khz oscillator amplifier circuit. input for the clock generator in bypass mode. i ? 55 71 ? nmi non-maskable interrupt i/o input, weak pull up 37 45 l3 vrc_ctrl voltage regulator external npn ballast base control pin ?2525p1 table 5. nexus pins system pin function pin number 144 lqfp 176 lqfp 208 mapbga evti nexus event in ? 37 t3 evto nexus event out ? 35 r3 mcko nexus msg clock out ? 33 t1 mdo[0] nexus msg data out ? 38 t5
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 17 mdo[1] nexus msg data out ? 40 p5 mdo[2] nexus msg data out ? 42 p4 mdo[3] nexus msg data out ? 44 l4 mse0 nexus msg start/end out ? 34 t2 table 5. nexus pins (continued) system pin function pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 18 2.4.6 functional ports a, b, c, d, e, f, g, h, i, j, k the functional port pins are listed in table 6 . table 6. port pin summary port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 emiosa[[22] sound fp23 siu dcu pwm/timer sound i/o m input, pull up 135 165 a1 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 emiosa[21] ? fp22 siu dcu pwm/timer ? i/o m none, none 136 166 b1 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 emiosa[20] ? fp21 siu dcu pwm/timer ? i/o m none, none 137 167 c1 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 emiosa[19] ? fp20 siu dcu pwm/timer ? i/o m none, none 138 168 c2 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 emiosa[18] ? fp19 siu dcu pwm/timer ? i/o m none, none 139 169 d1 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 emiosa[17] ? fp18 siu dcu pwm/timer ? i/o m none, none 140 172 d2 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 emiosa[15] ? fp17 siu dcu pwm/timer ? i/o m none, none 141 173 e1 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 emiosa[16] ? fp16 siu dcu pwm/timer ? i/o m none, none 142 174 e2
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 19 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 emiosb[23] scl_c fp15 siu dcu pwm/timer i 2 c_2 i/o m none, none 143 175 f1 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 emiosb[18] sda_c fp14 siu dcu pwm/timer i 2 c_2 i/o m none, none 144 176 f2 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 emiosb[20] ? fp13 siu dcu pwm/timer ? i/o m none, none 11 g1 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 emiosa[13] ? fp12 siu dcu pwm/timer ? i/o m none, none 22 g2 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 emiosa[12] ? fp11 siu dcu pwm/timer ? i/o m none, none 33 h1 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 emiosa[11] ? fp10 siu dcu pwm/timer ? i/o m none, none 44 h2 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 emiosa[10] ? fp9 siu dcu pwm/timer ? i/o m none, none 55 j2 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 emiosa[9] ? fp8 siu dcu pwm/timer ? i/o m none, none 66 h3 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 20 pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_a pdi1 ? ?siu can-a pdi ? i/o m none, none 106 130 t15 pb[1] pcr[17] option 0 option 1 option 2 option3 gpio[17] canrx_a pdi0 ? ?siu can-a pdi ? i/o s input, pull up 105 129 t14 pb[2] pcr[18] option 0 option 1 option 2 option3 gpio[18] txd_a ? ? ?siu lin_a ? ? i/o s none, none 112 140 r14 pb[3] pcr[19] option 0 option 1 option 2 option3 gpio[19] rxd_a ? ? ?siu lin_a ? ? i/o s input, pull up 111 139 r13 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_b ma0 ? ?siu spi_1 adc ? i/o m input, pull up 48 62 p8 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_b ma1 fabm ?siu spi_1 adc control i/o m input, pull down 49 63 n8 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_b ma2 abs[0] ?siu spi_1 adc control i/o s input, pull up 50 66 r7 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_a emiosb[22] ? ?siu spi_a pwm/timer ? i/o s none, none 46 56 p7 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 21 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_a emiosb[21] ? ?siu spi_a pwm/timer ? i/o m none, none 45 55 n7 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_a emiosb[20] ? ?siu spi_a pwm/timer ? i/o m input, pull up 44 54 t6 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] cnrx_b pdi2 emiosa[23] ?siu can-b pdi pwm/timer i/o s input, pull up 107 131 p13 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cntx_b pdi3 emiosa[16] ?siu can-b pdi pwm/timer i/o m none, none 108 132 n12 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_b emiosb[19] pcs_a2 ?siu lin_b pwm/timer spi_0 i/o s input, pull up 40 48 r6 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_b emiosb[18] pcs_a1 ?siu lin_b pwm/timer spi_0 i/o s none, none 41 49 p6 pb[14] ? ? reserved ? ? ? ? ? ? ? a11 pb[15] ? ? reserved ? ? ? ? ? ? ? ? pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] an[0] ? ? ?siu adc ? ? iainput, pull up 72 88 t13 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] an[1] ? ? ?siu adc ? ? iainput, pull up 71 87 t12 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 22 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] an[2] ? ? ?siu adc ? ? iainput, pull up 70 86 r12 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] an[3] ? ? ?siu adc ? ? iainput, pull up 69 85 p12 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] an[4] ? ? ?siu adc ? ? iainput, pull up 68 84 r11 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] an[5] ? ? ?siu adc ? ? iainput, pull up 67 83 p11 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] an[6] ? ? ?siu adc ? ? iainput, pull up 66 82 n11 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] an[7] ? ? ?siu adc ? ? iainput, pull up 65 81 r10 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] an[8] ? ? ?siu adc ? ? iainput, pull up 62 78 p10 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] an[9] ? ? ?siu adc ? ? iainput, pull up 61 77 n10 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 23 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] an[10] sound ? ?siu adc sound ? i/o s input, pull up 60 76 t9 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] an[11] ma0 pcs_b2 ?siu adc adc spi_b i/o s none, none 59 75 r9 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] an[12] ma1 pcs_b1 ?siu adc adc spi_b i/o s none, none 58 74 p9 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] an[13] ma2 pcs_b0 ?siu adc adc spi_b i/o s none, none 57 73 n9 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] an[14] extal32 ? ?siu adc osc ? i/o s none, none 56 72 t8 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] an[15] xtal32 ? ?siu adc osc ? i/o s none, none 55 71 r8 pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emiosb[23] ?siu smd ssd pwm/timer i/o smd none, none 73 89 r16 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emiosb[22] ?siu smd ssd pwm/timer i/o smd none, none 74 90 p16 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 24 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emiosb[21] ?siu smd ssd pwm/timer i/o smd none, none 75 91 p15 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emiosb[20] ?siu smd ssd pwm/timer i/o smd none, none 76 92 n16 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emiosb[19] ?siu smd ssd pwm/timer i/o smd none, none 79 95 n15 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emiosb[18] ?siu smd ssd pwm/timer i/o smd none, none 80 96 m15 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emiosb[17] ?siu smd ssd pwm/timer i/o smd none, none 81 97 m16 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 emiosb[16] ?siu smd ssd pwm/timer i/o smd none, none 82 98 k16 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siu smd ssd ? i/o smd none, none 83 99 j16 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 ? ?siu smd ssd ? i/o smd none, none 84 100 k15 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 25 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 ? ?siu smd ssd ? i/o smd none, none 85 101 n14 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 ? ?siu smd ssd ? i/o smd none, none 86 102 m14 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 ? ?siu smd ssd ? i/o smd none, none 89 105 l14 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 ? ?siu smd ssd ? i/o smd none, none 90 106 k14 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 ? ?siu smd ssd ? i/o smd none, none 91 107 m13 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 ? ?siu smd ssd ? i/o smd none, none 92 108 l13 pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 emiosa[15] ?siu smd ssd pwm/timer i/o smd none, none 93 109 j15 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 emiosa[14] ?siu smd ssd pwm/timer i/o smd none, none 94 110 g15 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 26 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 emiosa[13] ?siu smd ssd pwm/timer i/o smd none, none 95 111 j14 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 emiosa[12] ?siu smd ssd pwm/timer i/o smd none, none 96 112 k13 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 emiosa[11] ?siu smd ssd pwm/timer i/o smd none, none 99 115 j13 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 emiosa[10] ?siu smd ssd pwm/timer i/o smd none, none 100 116 h13 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 emiosa[9] ?siu smd ssd pwm/timer i/o smd none, none 101 117 h14 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 emiosa[8] ?siu smd ssd pwm/timer i/o smd none, none 102 118 g14 pe[8] ? ? reserved ? ? ? ? ? ? ? ? pe[9] ? ? reserved ? ? ? ? ? ? ? ? pe[10] ? ? reserved ? ? ? ? ? ? ? ? pe[11] ? ? reserved ? ? ? ? ? ? ? ? pe[12] ? ? reserved ? ? ? ? ? ? ? ? pe[13] ? ? reserved ? ? ? ? ? ? ? ? pe[14] ? ? reserved ? ? ? ? ? ? ? ? pe[15] ? ? reserved ? ? ? ? ? ? ? ? table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 27 pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emiosa[13] pdi4 emiosa[22] fp39 siu pwm/timer pdi pwm/timer i/o s input, pull up 113 143 a8 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emiosa[12] pdi5 emiosa[21] fp38 siu pwm/timer pdi pwm/timer i/o s none, none 114 144 b8 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siu nmi ? ? i/o s input, pull up 37 45 l3 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emiosa[11] pdi6 ? fp37 siu pwm/timer pdi ? i/o m input, pull up 115 145 c8 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emiosa[10] pdi7 ? fp36 siu pwm/timer pdi ? i/o m none, none 116 146 d8 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] emiosa[9] dcu_tag ? fp35 siu pwm/timer dcu ? i/o m input, pull up 117 147 a9 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] sda_a ? ? fp34 siu i 2 c_a ? ? i/o s input, pull up 120 150 b9 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] scl_a pcs_b2 ? fp33 siu i 2 c_a spi_b ? i/o s none, none 121 151 c9 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 28 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_b pcs_b1 rxd_b fp32 siu i 2 c_b spi_b lin_b i/o s input, pull up 122 152 t4 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_b pcs_b0 txd_b fp31 siu i 2 c_b spi_b lin_b i/o s none, none 123 153 r4 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] emiosa[16] pcs_c0 ? fp29 siu pwm/timer spi_c ? i/o m none, none 127 157 a14 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] emiosb[23] pcs_c1 ? fp28 siu pwm/timer spi_c ? i/o m input, pull up 128 158 a15 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] emiosb[16] pcs_c2 ? fp27 siu pwm/timer spi_c ? i/o m none, none 129 159 a16 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] sin_c cnrx_b ? fp26 siu spi_c can_b ? i/o m input, pull up 130 160 b16 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] sout_c cantx_b ? fp25 siu spi_c can_b ? i/o m none, none 131 161 c16 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] sck_c ? ? fp24 siu spi_c ? ? i/o f none, none 132 162 d16 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 29 pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_d sound fp7 siu dcu i 2 c_3 sound i/o m none, none 99 d3 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_d ? fp6 siu dcu i 2 c_3 ? i/o m none, none 10 10 e3 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 emiosb[19] ? fp5 siu dcu pwm/timer ? i/o m none, none 11 11 e4 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 emiosb[21] ? fp4 siu dcu pwm/timer ? i/o m none, none 12 12 f3 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 emiosb[17] ? fp3 siu dcu pwm/timer ? i/o m none, none 13 13 f4 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 emiosa[8] ? fp2 siu dcu pwm/timer ? i/o m none, none 14 14 g3 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? fp1 siu dcu ? ? i/o m none, none 15 15 g4 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? fp0 siu dcu ? ? i/o m none, none 16 16 h4 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 30 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? bp0 siu dcu ? ? i/o m input, pull up 17 17 j3 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? bp1 siu dcu ? ? i/o m input, pull up 18 18 k3 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? bp2 siu dcu ? ? i/o m none, none 19 19 j4 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? bp3 siu dcu ? ? i/o m none, none 20 20 k4 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] emiosa[23] sound emiosa[8] fp30 siu pwm/timer sound pwm/timer i/o s none, none 126 156 d10 pg[13] ? ? reserved ? ? ? ? ? ? ? ? pg[14] ? ? reserved ? ? ? ? ? ? ? ? pg[15] ? ? reserved ? ? ? ? ? ? ? ? ph[0] 4 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siu jtag ? ? i/o s input, pull up 36 43 r1 ph[1] 4 pcr[100] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siu jtag ? ? i/o s input, pull up 33 36 p2 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 31 ph[2] 4 pcr[101] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siu jtag ? ? i/o m output, none 34 39 n3 ph[3] 4 pcr[102] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siu jtag ? ? i/o s input, pull up 35 41 m3 ph[4] pcr[103] option 0 option 1 option 2 option 3 gpio[103] pcs_a0 emiosb[16] clkout ?siu spi_0 pwm/timer control i/o f none, none 47 61 r5 ph[5] pcr[104] option 0 option 1 option 2 option 3 gpio[104] vlcd ? ? ?siu lcd ? ? 21 21 ? ph[6] ? ? reserved ? ? ? ? ? ? ? ? ph[7] ? ? reserved ? ? ? ? ? ? ? ? ph[8] ? ? reserved ? ? ? ? ? ? ? ? ph[9] ? ? reserved ? ? ? ? ? ? ? ? ph[10] ? ? reserved ? ? ? ? ? ? ? ? ph[11] ? ? reserved ? ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ? ph[13] ? ? reserved ? ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? ? pj[0] pcr[105] option 0 option 1 option 2 option 3 gpio[105] pdi_de ? ? ?siu pdi ? ? i/o s none, none ?119 a2 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 32 pj[1] pcr[106] option 0 option 1 option 2 option 3 gpio[106] pdi_hsync ? ? ?siu pdi ? ? i/o s none, none ?120 a3 pj[2] pcr[107] option 0 option 1 option 2 option 3 gpio[107] pdi_vsync ? ? ?siu pdi ? ? i/o s none, none ?121 b3 pj[3] pcr[108] option 0 option 1 option 2 option 3 gpio[108] pdi_pclk ? ? ?siu pdi ? ? i/o m none, none ?122 a4 pj[4] pcr[109] option 0 option 1 option 2 option 3 gpio[109] pdi[0] cnrx_a ? ?siu pdi can-a ? i/o s input, pull up ?57 b4 pj[5] pcr[110] option 0 option 1 option 2 option 3 gpio[110] pdi[1] cntx_a ? ?siu pdi can-a ? i/o m none, none ?58 a5 pj[6] pcr[111] option 0 option 1 option 2 option 3 gpio[111] pdi[2] cnrx_b emiosa[22] ?siu pdi can-b pwm/timer i/o s input, pull up ?59 b5 pj[7] pcr[112] option 0 option 1 option 2 option 3 gpio[112] pdi[3] cntx_b emiosa[21] ?siu pdi can-b pwm/timer i/o m none, none ?60 a6 pj[8] pcr[113] option 0 option 1 option 2 option 3 gpio[113] pdi[4] ? ? ?siu pdi ? ? i/o s none, none ?125 b6 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 33 pj[9] pcr[114] option 0 option 1 option 2 option 3 gpio[114] pdi[5] ? ? ?siu pdi ? ? i/o s none, none ?126 c4 pj[10] pcr[115] option 0 option 1 option 2 option 3 gpio[115] pdi[6] ? ? ?siu pdi ? ? i/o s none, none ?127 c5 pj[11] pcr[116] option 0 option 1 option 2 option 3 gpio[116] pdi[7] ? ? ?siu pdi ? ? i/o s none, none ?128 d5 pj[12] pcr[117] option 0 option 1 option 2 option 3 gpio[117] pdi[8] emiosb[17] ? ?siu pdi pwm/timer ? i/o m none, none ?135 c6 pj[13] pcr[118] option 0 option 1 option 2 option 3 gpio[118] pdi[9] emiosb[20] ? ?siu pdi pwm/timer ? i/o m none, none ?136 d6 pj[14] pcr[119] option 0 option 1 option 2 option 3 gpio[119] pdi[10] emiosa[20] ? ?siu pdi pwm/timer ? i/o m none, none ?137 a7 pj[15] pcr[120] option 0 option 1 option 2 option 3 gpio[120] pdi[11] emiosa[19] ? ?siu pdi pwm/timer ? i/o m none, none ?138 b7 pk[0] pcr[121] option 0 option 1 option 2 option 3 gpio[121] pdi[12] emiosa[18] dcu_tag ?siu pdi pwm/timer dcu i/o m none, none ?141 c7 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 34 pk[1] pcr[122] option 0 option 1 option 2 option 3 gpio[122] pdi[13] emiosa[17] ? ?siu pdi pwm/timer ? i/o m none, none ?142 d7 pk[2] pcr[123] option 0 option 1 option 2 option 3 gpio[123] mcko pdi[10] ? ?siu nexus pdi ? i/o f none, none ?33 b12 pk[3] pcr[124] option 0 option 1 option 2 option 3 gpio[124] mseo pdi[11] ? ?siu nexus pdi ? i/o m none, none ?34 c12 pk[4] pcr[125] option 0 option 1 option 2 option 3 gpio[125] evto pdi[12] ? ?siu nexus pdi ? i/o m none, none ?35 d12 pk[5] pcr[126] option 0 option 1 option 2 option 3 gpio[126] evti pdi[13] ? ?siu nexus pdi ? i/o m none, none ?37 ? pk[6] pcr[127] option 0 option 1 option 2 option 3 gpio[127] mdo0 pdi[14] ? ?siu nexus pdi ? i/o m none, none ?38 b11 pk[7] pcr[128] option 0 option 1 option 2 option 3 gpio[128] mdo1 pdi[15] ? ?siu nexus pdi ? i/o m none, none ?40 c11 pk[8] pcr[129] option 0 option 1 option 2 option 3 gpio[129] mdo2 pdi[16] ? ?siu nexus pdi ? i/o m none, none ?42 d11 table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
pinout and signal descriptions mpc560xs microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 35 pk[9] pcr[130] option 0 option 1 option 2 option 3 gpio[130] mdo3 pdi[17] ? ?siu nexus pdi ? i/o m input, pull up ?44 a10 pk[10] pcr[131] option 0 option 1 option 2 option 3 gpio[131] sda_b emiosa[15] ? ?siu i 2 c_b pwm/timer ? i/o s none, none ?52 n6 pk[11] pcr[132] option 0 option 1 option 2 option 3 gpio[132] scl_b emiosa[14] ? ?siu i 2 c_b pwm/timer ? i/o s none, none ?53 n5 pk[12] ? ? reserved ? ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? ? 1 alternate functions are chosen by setting th e values of the pcr.pa bitfields inside the siu module. pcr.pa = 00 -> option 0; pc r.pa = 01 -> option 1; pcr.pa = 10 -> option 2; pcr. pa = 11-> option 3. this is intended to select th e output functions; to use one of the input fu nctions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 a=a, s=slow, m=medium, f=fa st, smd=stepper motor driver 3 reset configuration is given as i/o direction and pull, e.g., ?input, pullup?. 4 out of reset pins ph[0:3] are available as jtag pins (tck, tdi, tdo and tms respectively). it is up to the user to configure pi ns ph[0:3] when needed. table 6. port pin summary (continued) port pin pcr register alternate function 1 function special function peripheral i/o direction pad type 2 reset config. 3 pin number 144 lqfp 176 lqfp 208 mapbga
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 36 2.4.7 signal details table 7. signal details signal peripheral description abs[0] bam alternate boot select. gives an option to boot by downloading code via can or lin. an[0:15] analog-to-digital conversion (adc) inputs used to bring into the device sensor-based signals for a/d conversion. fabm force alternate boot mode. forces the device to boot from the external bus (can or lin). if not asserted, the device boots up from the lowest flash sector containing a valid boot signature. dcu_de display control unit indicates that valid pixels are present when high; otherwise low to allow a sub frame display for pixels. dcu_hsync, display control unit horizontal sync pulse for tft-lcd display. dcu_pclk display control unit output pixel clock for tft-lcd display dcu_r[0:7], dcu_g[0:7] dcu_b[0:7] display control unit red, green and blue color 8 bit pixel values for tft-lcd displays. dcu_tag display control unit high indicates certain pixels that can be called as tagged pixels, upon which internal crc has been calculated based on pixel values and pixel position. dcu_vsync display control unit vertic al sync pulse for tft-lcd display. pcs_a[0:2], pcs_b[0:2], pcs_c[0:2} dspi peripheral chip selects when device is in master mode; not used in slave modes. sck_a, sck_b, sck_c dspi spi clock signal - bi-directional. sin _a, sin _b, sin _c dspi spi data input signal. sout _a, sout _b, sout _c dspi spi data output signal. emiosa[0:23], emiosb[0:23] emios enhanced modular input output sy stem. 16+9 channel emios for timed input or output functions. cnrx_a, cnrx_b flexcan receive (rx) pins for the can bus transceiver. cntx_a, cntx_b flexcan transmit (tx) pins for the can bus transceiver. scl_a, scl_b, scl_c, scl_d i 2 c bidirectional serial clock compatible with i 2 c specifications. sda_a, sda_b, sda_c, sda_d i 2 c bidirectional serial data compatible with i 2 c specifications.
pinout and signal descriptions mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 37 tck jtag debug port serial clock as per jtag specifications. tdi jtag debug port serial data input port as per jtag standards specifications. tdo jtag debug port serial data output port as per jtag standards specifications. tms jtag debug port test mode select signal for the jtag tap controller state machine and indicates various state tr ansitions for the tap controller in the device. bp[0:3] lcd back plane signals from the l cd controlling the back plane reference voltage for the lcd display. fp[0:39] lcd front plane signals for lcd segments. evti nexus nexus2+ event input trigger. evto nexus nexus2+ event output trigger. mcko nexus output clock for the development tool mdo[0:3] nexus message output port pins that send information bits to the development tools for messages such as branch trace message (btm), ownership trace message (otm), data trace me ssage (dtm). only available in reduced port mode. mseo nexus output pin. indicates the start or end of the variable length message on the mdo pins. pdi[0:17] parallel display interface video/graphic data in various rgb modes input to the dcu. pdi_de parallel display interface input signal indicates the validity of pixel data on the input pdi data bus. for valid pixel data this is high, otherwise low. pdi_hsync parallel display interface input indicates the timing reference for the start of each frame line for the pdi input data. pdi_pclk parallel display interface output pixel clock for pdi. pdi_vsync parallel display interface input indicates the timing reference for the start of a frame for the pdi input data. rxd_a linflex-uart sci/lin receive data signal. this port is used to download the code for the bam boot sequence rxd_b linflex-uart sci/lin receive data signal. input pad for the lin sci module. connects to the internal lin second port. txd_a linflex-uart this port is used to download the code for the bam boot sequence txd_b linflex-uart sci/lin transmit data signal. transmit (output) port for the second lin module in the chip . sound sound generation logic (sgl) sound signal to the speaker/buzzer. table 7. signal details (continued) signal peripheral description
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice pinout and signal descriptions freescale semiconductor 38 ssd[0..5]_0 ssd[0..5]_1 ssd[0..5]_2 ssd[0..5]_3 ssd (stepper stall detect) interface bidirectional ssd inputs and control signals m[0:5]c0m m[0:5]c0p m[0:5]c1m m[0:5]c1p stepper motor control (smc) interface controls stepper motors in dual h bridge configuration. clkout clock generation module (cgm) output clock. it can be selected from several internal clocks of the device from the clock generation module. ma[0:2] adc these three control bits are output to enable the selection for an external analog mux for expansion channels. table 7. signal details (continued) signal peripheral description
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 39 3 electrical characteristics this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by internal pull up and pull down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 3.1 absolute maximum ratings table 8. absolute maximum ratings symbol parameter conditions value unit min max v dda sr voltage on vdda pin (adc reference) with respect to ground (v ssa ) -0.3 +5.5 v relative to v dd v dd -0.3 v dd +0.3 v ssa sr voltage on vssa (adc refere nce) pin with respect v ss v ss -0.1 v ss +0.1 v v ddpll cc voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) 1.08 1.32 v relative to v dd v dd -0.3 v dd +0.3 v sspll sr voltage on vssmc (stepper motor supply ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v ddr sr voltage on vddr pin (regulator supply) with respect to ground (v ssr ) -0.3 +5.5 v relative to v dd v dd -0.3 v dd +0.3 v ssr sr voltage on vssr (regulator ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v dd12 cc voltage on vdd12 pin with respect to ground (v ss12 ) 1.08 1.4 v v ss12 cc voltage on vss12 pin with respect to v ss v ss -0.1 v ss +0.1 v v dde_a 1 sr voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) -0.3 +5.5 v v dde_b 1 sr voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) -0.3 +5.5 v v dde_c 1 sr voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) -0.3 +5.5 v v dde_e 1 sr voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) -0.3 +5.5 v
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 40 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 41 3.1.1 recommended operating conditions table 9. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max v dda 1 sr voltage on vdda pin (adc reference) with respect to ground (v ss ) +3.0 +3.6 v relative to v dd v dd -0.1 v dd +0.1 v ssa sr voltage on vssa (adc reference) pin with respect v ss v ss -0.1 v ss +0.1 v v ddpll cc voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) 1.08 1.32 v v sspll sr voltage on vssmc (stepper motor supply ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v ddr 2 sr voltage on vddr pin (regulator supply) with respect to ground (v ssr ) +3.0 +3.6 v relative to v dd v dd -0.1 v dd +0.1 v ssr sr voltage on vssr (regulat or ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v dd12 3,4 cc voltage on vdd12 pin with respect to ground (v ss12 ) 1.08 1.4 v v ss12 cc voltage on vss12 pin with respect to v ss v ss -0.1 v ss +0.1 v v dd 5,6,7 sr voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) +3.0 +3.6 v v ss 8 sr i/o supply ground 0 0 v v dde_a sr voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) +3.0 +3.6 v v dde_b sr voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) +3.0 +3.6 v v dde_c 9 sr voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) +3.0 +3.6 v v dde_e sr voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) +3.0 +3.6 v v ddma sr voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) +3.0 +3.6 v v ddmb sr voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) +3.0 +3.6 v v ddmc sr voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) +3.0 +3.6 v v ssosc sr voltage on vssosc (oscillator ground) pin with respect to v ss 00v
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 42 v lcd sr voltage on vlcd (lcd supply) pin with respect to v ss 0v dde_a +0.3 v tv dd sr v dd slope to ensure correct power up 10 0.25 v/s t a sr ambient temperature under bias -40 +105 c t j sr junction temperature under bias -40 +150 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 200 f capacitance must be connected between v ddr and v ss12 . 3 v dd12 cannot be used to drive any external component. 4 each v dd12 /v ss12 supply pair should have a 10 f capacitor. absolute combi ned maximum capacitance is 40 f. 5 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 6 100 nf capacitance needs to be provided between each v dd /v ss pair 7 full electrical specification cannot be guaranteed when vo ltage drops below 3.0v. in particular, adc electrical characteristics and i/o?s dc electrical specification may not be guaranteed. when voltage drops below v lv d h v l device is reset. 8 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. 9 v dde_c should not be less than v dda . 10 guaranteed by device validation table 10. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max v dda 1 sr voltage on vdda pin (adc reference) with respect to ground (v ss ) +4.5 +5.5 v voltage drop 2 +3.0 +5.5 relative to v dd v dd -0.1 v dd +0.1 v ssa sr voltage on vssa (adc reference) pin with respect v ss v ss -0.1 v ss +0.1 v v ddpll cc voltage on vddpll (1.2 v pll supply) pin with respect to ground (v sspll ) 1.08 1.32 v v sspll sr voltage on vssmc (stepper motor supply ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v ddr 3 sr voltage on vddr pin (regulator supply) with respect to ground (v ssr ) +4.5 +5.5 v voltage drop 2 +3.0 +5.5 relative to v dd v dd -0.1 v dd +0.1 v ssr sr voltage on vssr (regulator ground) pin with respect to v ss v ss -0.1 v ss +0.1 v v dd12 4,5 cc voltage on vdd12 pin with respect to ground (v ss12 ) 1.08 1.4 v table 9. recommended operating conditions (3.3 v) (continued) symbol parameter conditions value unit min max
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 43 v ss12 cc voltage on vss12 pin with respect to v ss v ss -0.1 v ss +0.1 v v dd 6,7 sr voltage on vdd pins (vdde_a, vdde_b, vdde_c, vdde_e, vddma, vddmb, vddmc) with respect to ground (v ss ) voltage drop 2 +4.5 +5.5 v v ss 8 sr i/o supply ground 0 0 v v dde_a sr voltage on vdde_a (i/o supply) pin with respect to ground (v sse_a ) +4.5 +5.5 v v dde_b sr voltage on vdde_b (i/o supply) pin with respect to ground (v sse_b ) +4.5 +5.5 v v dde_c 9 sr voltage on vdde_c (i/o supply) pin with respect to ground (v sse_c ) +4.5 +5.5 v v dde_e sr voltage on vdde_e (i/o supply) pin with respect to ground (v sse_e ) +4.5 +5.5 v v ddma sr voltage on vddma (stepper motor supply) pin with respect to ground (v ssma ) +4.5 +5.5 v v ddmb sr voltage on vddmb (stepper motor supply) pin with respect to ground (v ssmb ) +4.5 +5.5 v v ddmc sr voltage on vddmc (stepper motor supply) pin with respect to ground (v ssmc ) +4.5 +5.5 v v ssosc sr voltage on vssosc (oscillator ground) pin with respect to v ss 00v v lcd sr voltage on vlcd (lcd supply) pin with respect to v ss 0v dde_a +0.3 v tv dd sr v dd slope to ensure correct power up 10 0.25 v/s t a sr ambient temperature under bias -40 +105 c -40 +105 t j sr junction temperature under bias -40 +150 1 100 nf capacitance needs to be provided between v dda /v ssa pair. 2 full functionality cannot be guaranteed when voltage drops below 4.5 v. in particular, i/o dc and adc electrical characteristics may not be guaranteed below 4.5 v during the voltage drop sequence. 3 200 f capacitance must be connected between v ddr and v ss12 . 4 v dd12 cannot be used to drive any external component. 5 each v dd12 /v ss12 supply pair should have a 10 f capacitor. absolute combi ned maximum capacitance is 40 f. 6 v dd refers collectively to i/o voltage supplies, i.e., v dde_a , v dde_b , v dde_c , v dde_e , v ddma , v ddmb and v ddmc . 7 100 nf capacitance needs to be provided between each v dd /v ss pair 8 v ss refers collectively to i/o voltage supply grounds, i.e., v sse_a , v sse_b , v sse_c , v sse_e , v ssma , v ssmb and v ssmc ) unless otherwise noted. 9 v dde_c should not be less than v dda . 10 guaranteed by device validation table 10. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 44 3.2 thermal characteristics table 11. thermal characteristics for 144-pin lqfp 1 1 thermal characteristics are targets based on simulation t hat are subject to change per device characterization. symbol parameter conditions value unit r ja cc junction to ambient natural convection 2 2 junction-to-ambient thermal resistance determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board - 1s 50 c/w r ja cc junction to ambient natural convection 2 four layer board - 2s2p 41 c/w r jma cc junction to ambient 2 @200 ft./min., single layer board - 1s 41 c/w r jma cc junction to ambient 2 @200 ft./min., four layer board- 2s2p 35 c/w r jb cc junction to board 3 3 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. 29 c/w r jctop cc junction to case 4 4 junction-to-case at the top of the package determ ined using mil-std 883 met hod 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. 10 c/w jt cc junction to package top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. 2c/w table 12. thermal characteristics for 176-pin lqfp 1 1 thermal characteristics are targets based on simulation t hat are subject to change per device characterization. symbol parameter conditions value unit r ja cc junction to ambient natural convection 2 2 junction-to-ambient thermal resistance determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board - 1s 43 c/w r ja cc junction to ambient natural convection 2 four layer board - 2s2p 35 c/w r jma cc junction to ambient 2 @200 ft./min., single layer board - 1s 35 c/w r jma cc junction to ambient 2 @200 ft./min., four layer board - 2s2p 30 c/w r jb cc junction to board 3 3 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. 24 c/w r jctop cc junction to case (top) 4 4 junction-to-case at the top of the package determ ined using mil-std 883 met hod 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. 9c/w jt cc junction to package top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. 2c/w
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 45 3.2.1 general notes for specifications at maximum junction temperature an estimate of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ja * p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd 51 series of standards to provide consistent values for estimations and comparisons. th e difference between the values determined fo r the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a grou nd plane (2s2p), demonstrate that the effective thermal resistan ce is not a constant. the therma l resistance depends on the: ? construction of the application board (number of planes) ? effective size of the boar d which cools the component ? quality of the thermal and elect rical connections to the planes ? power dissipated by adjacent components connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between the vias leave the planes virtually disconnected, the thermal pe rformance is also greatly reduced. as a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. the value obtained on a board with the internal planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm2 the thermal performance of any component depends on the power dissipation of the surrounding components. in addition, the ambient temperature varies widely within the application. for many natural conv ection and especially cl osed box applications, the board temperature at the perimeter (edge ) of the package is approxim ately the same as the loca l air temperature near the device. specifying the local ambi ent conditions explicitly as th e board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: t j = t b + (r jb * p d ) eqn. 2 where: t b = board temperature for the package perimeter ( o c) r jb = junction-to-board thermal resistance ( o c/w) per jesd51-8s p d = power dissipation in the package (w) when the heat loss from the package case to the air does not factor in to the calculation, an accep table value for the junction temperature is predictable. ensure the appl ication board is similar to the thermal te st condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junctio n-to-case thermal resistance pl us a case-to-ambient thermal resistance: r ja = r jc + r ca eqn. 3
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 46 where: r ja = junction to ambient thermal resistance ( o c/w) r jc = junction to case thermal resistance ( o c/w) r ca = case to ambient thermal resistance ( o c/w) r jc s device related and is not affected by other factors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ca . for example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. for most pack ages, a better model is required. a more accurate two-resistor thermal model can be construc ted from the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case thermal resistance descri bes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the pr inted circuit board. this model can be used to generate simple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of th e device in the application on a prototyp e board, use the thermal characterization parameter ( jt ) to determine the junction temperature by measuring the temperature at the top cente r of the package case using the following equation: t j = t t + ( jt x p d ) eqn. 4 where: t t = thermocouple temperature on top of the package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compli ance with the jesd51-2 specificat ion using a 40-gauge type t thermocouple epoxied to the top center of the package case. positio n the thermocouple so that the thermocouple junction rests on the package. place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocoup le wire flat against the package case to avoi d measurement errors caused by the cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org .
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 47 3.3 emi (electromagnetic interference) characteristics 3.4 power management 3.4.1 voltage regulator electrical characteristics the internal voltage regulat or requires an external npn (bcp56 or bcp68) ballast to be connected as shown in figure 5 as well as an external capacitance (c reg ) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possible to the associat ed pins. care should also be taken to lim it the serial inductance of the board to less than 15 nh. for the MPC5606S micr ocontroller , 10 f should be pl aced between each of the three v dd12 /v ss12 supply pairs and also between the v ddpll /v sspll pair. additionally, 200 f should be placed between the v ddr pin and the adjacent v ss pin. v ddr = 3.0 v to 3.6 v / 4.5 v to 5.5 v, t a = -40 to 105 c, unless otherwise specified. figure 5. external npn ballast connections table 13. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 1995-03. symbol parameter value unit min typ max ? sr scan range tbd tbd tbd mhz ? sr operating frequency tbd tbd tbd mhz ? sr vdd12, vddpll operating voltages tbd tbd tbd v ? sr vdd, vdda operating voltages tbd tbd tbd v ? sr maximum amplitude tbd tbd tbd dbuv ? sr operating temperature tbd tbd tbd o c vrc_ctrl v ddr v dd12
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 48 3.4.2 voltage monitor electrical characteristics the device implements a power on reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the v dd and the v dd12 voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 table 14. voltage regulator electrical characteristics 1 1 all values in this table are preliminary. no. symbol parameter conditions min max unit 1v ddr sr power supply 3.0 5.5 v 2t j sr junction temperature -40 150 c 3i reg cc current consumption reference included, @ 55 c no load @ full load ? 2 11 ma 4i l cc output current capacity dc load current ? 200 ma 5v dd12 cc output voltage (value @ i l = 0 @ 27c) pre-trimming sigma < 7 mv ? 1.330 v post-trimming 1.270 1.280 output voltage (value @ i l = imax) post-trimming 1.145 ? 6 sr external decoupling/stabilit y capacitor 4 capacitances of 10 f each 10 * 4 f esr of external cap 0.05 0.2 ohm 1 bond wire r + 1 pad r 0.2 1 ohm 7l bond cc bonding inductance for bipolar base control pad 0 15 nh 8 cc power supply rejection @ dc @ no load cload = 10 f * 4 ? -30 db @ 200 khz @ no load -100 @ dc @ 400 ma -30 @ 200 khz @ 400 ma -30 9 cc load current transient cload = 10 f * 4 ? 10% to 90% of i l (max) in 100 ns 10 t su cc start-up time after input supply stabilizes 2 2 time after the input supply to the voltage regulator has ramped up (vddr) and the voltage regulator has asserted the power ok signal. cload = 10 f * 4 ? 500 s
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 49 3.4.3 low voltage domain power consumption table 16 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 15. low voltage monitor electrical characteristics symbol parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 / +105c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v porh cc power-on reset threshold t a = 25c, after trimming 1.5 ? 2.7 v v lv d h v 3 h cc lvdhv3 low voltage detector high threshold ? ? 2.8 v lv d h v3 l cc lvdhv3 low voltage detector low threshold 2.7 ? ? v lv d h v 5 h cc lvdhv5 low voltage detector high threshold ? ? 4.37 v lv d h v5 l cc lvdhv5 low voltage detector low threshold 4.2 ? ? v lvd lv c o r h cc lvdlvcor low voltage detector high threshold ? ? 1.185 v lv d lv c o r l cc lvdlvcor low voltage detector low threshold 1.095 ? ? table 16. dc electrical characteristics symbol parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 / +125 c value 2 2 all values need to be confirmed during device validation. unit min typ max i ddmax sr maximum current ? ? 135 ma i ddrun 3 3 value is for maximum peripherals turned on. may vary si gnificantly based on differ ent configurations, active peripherals, operating frequency, etc. cc run mode current ? 130 ? ma i ddwait cc wait mode current ? 30 ? ma i ddhalt cc halt mode current 4.5 ? 12 ma i ddstop cc stop mode current irc 16 mhz oscillator off ? 1.5 ? ma i ddstop cc stop mode current hpvreg off ? 800 ? a i ddstop cc stop mode current irc 16 mhz oscillator on ? 4 ? ma i ddstdby cc standby mode current irc 16 mhz oscillator off ? 29 ? a i ddstdby cc standby mode current irc 16 mhz oscillator on ? 300 ? a
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 50 3.5 dc electrical specifications 3.6 i/o pad electrical characteristics 3.6.1 i/o pad types the device provides four main i/o pad types depe nding of the associated alternate functions: ? slow pads are the most common pads, providing a good compromi se between transition time and low electromagnetic emission. ? medium pads provide fast enough transition for the serial communication channels with controlled current to reduce electromagnetic emission. ? fast pads provide maximum speed. there are used for improved nexus debugging capability. medium and fast pads can use slow configuration to reduce elect romagnetic emission, at the cost of reducing ac performance. 3.6.2 i/o input dc characteristics table 17 provides input dc electrical ch aracteristics as described in figure 6 . figure 6. i/o input dc electri cal characteristics definition table 17. i/o input dc el ectrical characteristics symbol parameter conditions 1 value 2 unit min typ max v ih sr input high level cmos schmitt trigger 0.65v dd v dd +0.4 v v il sr input low level cmos schmitt trigger -0.4 0.35v dd v hys cc 3 input hysteresis cmos schmitt trigger 0.1v dd v il v in v ih v internal v dd v hys (siu register)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 51 3.6.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 18 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 19 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 20 provides output driver char acteristics for i/o pads when in medium configuration. ? table 21 provides output driver char acteristics for i/o pads wh en in fast configuration. 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c. 2 all values need to be confirmed during device validation. 3 parameter value guaranteed by design. table 18. i/o pull-up/pull-down dc electrical characteristics symbol parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 to +105c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max |i wpu | cc weak pull-up current absolute value 10 ? a |i wpd | cc weak pull-down current absolute value 10 ? table 19. slow configuration output buffer electrical characteristics symbol parameter conditions 1 value 2 unit min typ max v oh cc output high level slow configuration push pull, i oh = -2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.8v dd v push pull, i oh = -2ma, v dd = 5.0v 10%, ipp_hve = 1 3 0.8v dd push pull, i oh = -1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) v dd -0. 8 v ol cc output low level slow configuration push pull, i ol = 2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.1v dd v push pull, i ol = 2ma, v dd = 5.0v 10%, ipp_hve = 1 3 0.1v dd push pull, i ol = 1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) 0.5
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 52 t tr cc 4 output transition time output pin 5 slow configuration c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 50 6 ns c l = 50pf, v dd = 5.0v 10%, ipp_hve = 0 100 6 c l = 100pf, v dd = 5.0v 10%, ipp_hve = 0 125 4 c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 40 6 c l = 50pf, v dd = 3.3v 10%, ipp_hve = 1 50 6 c l = 100pf, v dd = 3.3v 10%, ipp_hve = 1 75 4 i tr50 cc 4 current slew at c l = 50pf slow configuration recommended configuration at v dd = 5.0v 10%, ipp_hve = 0, v dd = 3.3v 10%, ipp_hve = 1 2ma/ns v dd = 5.0v 10%, ipp_hve = 1 7 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 to +105c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 this is a transient config uration during power-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 4 data based on characterization results, not tested in production 5 c l calculation should include device and package capacitances (c pkg < 5pf). 6 data based on simulation results, not tested in production table 20. medium configuration output buffer electrical characteristics symbol parameter conditions 1 value 2 unit min typ max v oh cc output high level medium configuration push pull, i oh = -2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.8v dd v push pull, i oh = -1ma, v dd = 5.0v 10%, ipp_hve = 1 3 0.8v dd push pull, i oh = -1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) v dd -0.8 table 19. slow configuration output buffer electrical characteristics (continued) symbol parameter conditions 1 value 2 unit min typ max
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 53 v ol cc output low level medium configuration push pull, i ol = 2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.1v dd v push pull, i ol = 1ma, v dd = 5.0v 10%, ipp_hve = 1 3 0.1v dd push pull, i ol = 1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) 0.5 t tr cc 4 output transition time output pin 5 medium configuration c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 10 ns c l = 50pf, v dd = 5.0v 10%, ipp_hve = 0 20 c l = 100pf, v dd = 5.0v 10%, ipp_hve = 0 40 c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 12 c l = 50pf, v dd = 3.3v 10%, ipp_hve = 1 25 c l = 100pf, v dd = 3.3v 10%, ipp_hve = 1 40 i tr50 cc 4 current slew at c l = 50pf medium configuration recommended configuration at v dd = 5.0v 10%, ipp_hve = 0 v dd = 3.3v 10%, ipp_hve = 1 7ma/ns v dd = 5.0v 10%, ipp_hve = 1 16 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 to +105c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 this is a transient config uration during power-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 4 data based on characterization results, not tested in production 5 c l calculation should include device and package capacitance (c pkg < 5pf). table 20. medium configuration output buffer electrical characteristics (continued) symbol parameter conditions 1 value 2 unit min typ max
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 54 table 21. fast configuration output buffer electrical characteristics symbol parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 to +105c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v oh cc output high level fast configuration push pull, i oh = -14ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.8v dd v push pull, i oh = -7ma, v dd = 5.0v 10%, ipp_hve = 1 3 3 this is a transient config uration during power-up. all pads but reset and nexus output (mdox, evto, mck) are configured in input or in high impedance state. 0.8v dd push pull, i oh = -11ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) v dd -0.8 v ol cc output low level fast configuration push pull, i ol = 14ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.1v dd v push pull, i ol = 7ma, v dd = 5.0v 10%, ipp_hve = 1 3 0.1v dd push pull, i ol = 11ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) 0.5 t tr cc 4 4 data based on characterization results, not tested in production output transition time output pin 5 fast configuration 5 c l calculation should include device and package capacitance (c pkg < 5pf). c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 4ns c l = 50pf, v dd = 5.0v 10%, ipp_hve = 0 6 c l = 100pf, v dd = 5.0v 10%, ipp_hve = 0 12 c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 4 c l = 50pf, v dd = 3.3v 10%, ipp_hve = 1 7 c l = 100pf, v dd = 3.3v 10%, ipp_hve = 1 12 i tr50 4 cc current slew at c l = 50pf fast configuration v dd = 5.0v 10%, ipp_hve = 0 (recommended configuration) 55 ma/n s v dd = 3.3v 10%, ipp_hve = 1 (recommended configuration) 40 v dd = 5.0v 10%, ipp_hve = 1 100
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 55 3.6.4 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 22 . table 23 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment should remain below the i dynseg maximum value. table 22. i/o supply segment package supply segment a 1 1 lcd pad segment containing pad supplies v dde_a b 2 2 misc. pad segment containing pad supplies v dde_b c 3,4 3 adc pad segment containing pad supplies v dde_c 4 adc v dda and v dde_c should be at the same voltage level d 5 5 stepper motor pad segment containing i/o supplies v ddma , v ddmb , v ddmc e 6 6 misc pad segment containing pad supplies v dde_e 144 lqfp pins 1 - 21 pins 113 - 144 pins 22 - 52 pins 53 - 72 pins 73 - 102 pins 103 - 112 176 lqfp pins 1 - 21 pins 143 - 176 pins 22 - 68 pins 69 - 88 pins 89 - 118 pins 119 - 142 table 23. i/o consumption symbol parameter conditions 1 value 2 unit min typ max i swtslw cc 3 dynamic i/o current for slow configuration c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 20 ma c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 16 i swtmed cc 3 dynamic i/o current for medium configuration c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 29 ma c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 17 i swtfst 3 cc 3 dynamic i/o current for fast configuration c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 110 ma c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 50
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 56 i rmsslw cc rms i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, ipp_hve = 0 2.3 3 ma c l = 25 pf, 4 mhz v dd = 5.0 v 10%, ipp_hve = 0 3.2 3 c l = 100 pf, 2 mhz v dd = 5.0 v 10%, ipp_hve = 0 6.6 4 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, ipp_hve = 1 1.6 3 c l = 25 pf, 4 mhz v dd = 3.3 v 10%, ipp_hve = 1 2.3 3 c l = 100 pf, 2 mhz v dd = 3.3 v 10%, ipp_hve = 1 4.7 4 i rmsmed cc average i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, ipp_hve = 0 6.6 3 ma c l = 25 pf, 4 mhz v dd = 5.0 v 10%, ipp_hve = 0 13.4 3 c l = 100 pf, 2 mhz v dd = 5.0 v 10%, ipp_hve = 0 18.3 4 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, ipp_hve = 1 5.0 3 c l = 25 pf, 4 mhz v dd = 3.3 v 10%, ipp_hve = 1 8.5 3 c l = 100 pf, 2 mhz v dd = 3.3 v 10%, ipp_hve = 1 11.0 4 i rmsfst cc average i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0v 10%, ipp_hve = 0 22.0 3 ma c l = 25 pf, 4 mhz v dd = 5.0v 10%, ipp_hve = 0 33.0 3 c l = 100 pf, 2 mhz v dd = 5.0v 10%, ipp_hve = 0 56.0 4 c l = 25 pf, 2 mhz v dd = 3.3v10%, ipp_hve = 1 14.0 3 c l = 25 pf, 4 mhz v dd = 3.3 v 10%, ipp_hve = 1 20.0 3 c l = 100 pf, 2 mhz v dd = 3.3 v 10%, ipp_hve = 1 25.0 4 i dynseg sr sum of all the dynamic and static i/o current within a supply segment v dd = 5.0 v 10%, ipp_hve = 0 110 ma v dd = 3.3 v 10%, ipp_hve = 1 65 i avgseg sr sum of all the stat ic i/o current within a supply segment v dd = 5.0 v 10%, ipp_hve = 0 70 ma v dd = 3.3 v 10%, ipp_hve = 1 65 table 23. i/o consumption (continued) symbol parameter conditions 1 value 2 unit min typ max
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 57 3.7 reset electrical characteristics the device implements a dedicat ed bidirectional reset pin. figure 7. start-up reset requirements figure 8. noise filtering on reset signal 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 data based on simulation results, not tested in production 4 data based on characterization results, not tested in production v il v dd t rstrem device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 58 table 24. reset electrical characteristics symbol parameter conditions 1 1 v dd = 3.3v 10% / 5.0v 10%, t a = -40 / +105 o c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr input high level cmos schmitt trigger 0.65v dd v dd +0.4 v v il sr input low level cmos schmitt trigger -0.4 0.35v dd v v hys cc 3 3 data based on characterization results, not tested in production input hysteresis cmos schmitt trigger 0.1v dd v v ol cc 4 4 guaranteed by design simulation. output low level push pull, i ol = 2ma, v dd = 5.0v 10%, ipp_hve = 0 (recommended) 0.1v dd v push pull, i ol = 1ma, v dd = 5.0v 10%, ipp_hve = 1 5 5 this is a transient co nfiguration during power-up, up to the end of reset phase2 (refer to rgm module section of the reference manual). 0.1v dd push pull, i ol = 1ma, v dd = 3.3v 10%, ipp_hve = 1 (recommended) 0.5 t tr cc 4 output transition time output pin 6 medium configuration 6 c l calculation should include device and package capacitance (c pkg < 5pf). c l = 25pf, v dd = 5.0v 10%, ipp_hve = 0 10 ns c l = 50pf, v dd = 5.0v 10%, ipp_hve = 0 20 c l = 100pf, v dd = 5.0v 10%, ipp_hve = 0 40 c l = 25pf, v dd = 3.3v 10%, ipp_hve = 1 12 c l = 50pf, v dd = 3.3v 10%, ipp_hve = 1 25 c l = 100pf, v dd = 3.3v 10%, ipp_hve = 1 40 w frst sr reset input filtered pulse - 40 ns w nfrs t sr reset input not filtered pulse 1000 - - ns |i wpu |cc 4 weak pull-up current absolute value 10 a
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 59 3.8 main oscillator electrical characteristics the device provides an oscillator/resonator driver. figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. figure 9. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. c l c l crystal xtal extal r p resonator xtal extal device device device xtal extal i r v dd
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 60 figure 10. main oscillator electrical characteristics table 25. main oscillator electrical characteristics symbol parameter conditions 1 value 2 unit min typ max f xoschs sr oscillator frequency 4.0 ? 16.0 mhz g mxoschs cc 3 oscillator transconductance v dd = 3.3 v 10%, oscillator_margin = 0 4.11 5.59 7.38 ma/v v dd = 5.0 v 10%, oscillator_margin = 0 3.67 5.04 6.73 v dd = 3.3 v 10%, oscillator_margin = 1 4.93 6.70 8.86 v dd = 5.0 v 10%, oscillator_margin = 1 4.54 6.22 8.31 v xoschs cc 3 oscillation amplitude f osc = 4 mhz, v dd = 3.3 v 10% 2.51 ? ? v f osc = 16 mhz, v dd = 3.3 v 10% 1.68 ? ? f osc = 4 mhz, v dd = 5.0 v 10% 4.74 ? ? f osc = 16 mhz, v dd = 5.0 v 10% 3.02 ? ? v xoschsop cc 3 oscillation operating point v dd = 3.3 v 10% v extal 0.894 ? 1.143 v v xtal 0.894 ? 1.146 v dd = 5.0 v 10% v extal 0.904 ? 1.166 v xtal 0.904 ? 1.169 v xoschsop v dd t xoschssu v ddmin v xtal v xoschs valid internal clock 90% 10% 1/f xoschs
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 61 3.9 low power oscillator electrical characteristics the device provides a low power oscillator/resonator driver. figure 11. crystal oscillator and resonator connection scheme note pc[14]/pc[15] must not be directly used to drive ex ternal circuits. i xoschs cc 3 oscillator consumption f osc = 4 mhz ? ? 2.43 ma f osc = 16 mhz ? ? 2.52 t xoschssu cc 3 oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ??6.0ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65v dd v dd +0.4 v v il sr input low level cmos schmitt trigger oscillator bypass mode -0.4 0.35v dd v 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 data based on simulation results, not tested in production table 25. main oscillator electrical characteristics (continued) symbol parameter conditions 1 value 2 unit min typ max c y c x crystal pc[14] pc[15] r f resonator pc[14] pc[15] device device
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 62 figure 12. low power oscillator electrical characteristics 3.10 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. table 26. low power oscillator electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max f xosclp sr oscillator frequency 32 - 40 khz v xosclp cc 3 3 granted by device validation oscillation amplitude v dd =3.3v 10%, 1.12 1.33 1.74 v v dd =5.0v 10%, 1.12 1.37 1.74 i xosclp cc 3 oscillator consumption 5 a t xosclpsu cc 3 oscillator start-up time 2 s v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65v dd v dd +0.4 v v il sr input low level cmos schmitt trigger oscillator bypass mode -0.4 0.35v dd v v dd t xosclpsu v ddmin v xtal v xosclp valid internal clock 90% 10% 1/f xosclp
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 63 3.11 main rc oscillator electrical characteristics the device provides a 16 mhz internal rc oscillator. this is used as the default clock at the power-up of the device. table 27. fmpll electrical characteristics symbol parameter conditions 1 1 v ddpll = 1.2 v 10%, t a = -40 to +105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f pllin sr pll reference clock 3 3 pllin clock retrieved directly from xo schs clock. input characteristics ar e granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and pllin . 464mhz pllin sr pll reference clock duty cycle 3 40 60 % f pllout cc 4 4 data based on device simulation. pll output clock frequency 16 64 mhz f cpu cc 4 system clock frequency 64 5 5 f cpu 64 mhz can be achieved only at up to 105 c mhz t lock cc 4 pll lock time stable oscillator (f pllin = 16 mhz) 200 s t pkjit cc 4 pll jitter (pk to pk) f pllin = 16 mhz (resonator) 500 ps t ltjit cc 4 pll long term jitter f pllin = 16 mhz (resonator) 1.5 ns i pll cc 6 6 data based on characterization results, not tested in production oscillator consumption t a = 25c 4 ma table 28. main rc oscillator electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f rcm cc 3 3 guaranteed by device simulation, not tested in production rc oscillator high frequency t a = 25 c, trimmed 16 mhz i rcmrun cc 3 rc oscillator high frequency current in running mode t a = 25 c, trimmed 200 a i rcmpwd cc 3 rc oscillator high frequency current in power down mode t a = 25 c 10 a rcmtri m cc 3 rc oscillator precision after trimming of f rc t a = 25 c -1 +1 % rcmvar cc 4 4 guaranteed by device characterization, not tested in production rc oscillator variation in temperature and supply with respect to f rc at t a = 55 c in high-frequency configuration -5 +5 %
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 64 3.12 low power rc oscillator electrical characteristics the device provides a low power internal rc oscillator. this can be used as the reference clock for the rtc module. 3.13 flash memory electrical characteristics table 29. low power rc oscillator electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f rcl cc 3 3 guaranteed by device simulation, not tested in production rc oscillator low frequency t a = 25 c, trimmed 128 khz i rcl cc 3 rc oscillator low frequency current t a = 25 c, trimmed 5 a rcltrim cc 3 rc oscillator precision after trimming of f rcl t a = 25 c -2 +2 % rclvar 3 cc 3 rc oscillator variation in temperature and supply with respect to f rc at t a = 55 c in high frequency configuration high frequency configuration -10 +10 % table 30. program and erase specifications symbol parameter min value typical value 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/er ase cycles, 25 c, typical supply voltage. max 3 3 the maximum program & erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. unit t dwprogram double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?22500 s t 16kpperase 16 kb block pre-program and erase time ? 500 5000 ms t 32kpperase 32 kb block pre-program and erase time ? 600 5000 ms t 128kpperase 128 kb block pre-program and erase time ? 1300 7500 ms
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 65 3.14 analog to digital converte r (adc) electrical characteristics the device provides a 10-bit successive approximatio n register (sar) analog to digital converter. table 31. flash module life symbol parameter conditions value unit min typ p/e number of program/erase cycles per block for 16 kbyte blocks over the operating temperature range (t j ) ? 100,000 ? cycles p/e number of program/erase cycles per block for 32 kbyte blocks over the operating temperature range (t j ) ? 10,000 100,000 (tbd) cycles p/e number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) ? 1,000 100,000 (tbd) cycles retention minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over duration of applic ation, not to exceed re commended product operating temperature range. blocks with 0 - 1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 1 - 5 (tbd) ?years
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 66 figure 13. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dda / 1024
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 67 in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330k is obtained (r eq = 1 / (fc*c s ), where fc represents the c onversion rate at the consid ered channel). to minimize th e error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 5 : eqn. 5 equation 5 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 14. input equivalent circuit (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb < r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 68 figure 15. input equivalent circuit (extended channels) a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 14 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 16. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 )
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 69 eqn. 6 equation 6 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 7 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 8 : eqn. 8 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 9 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 10 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 11 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 11 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. 1 r sw r ad + () = c p c s ? c p c s + --------------------- ? 1 r sw r ad + () < c s t s ? ? () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 2 ? 10 r l c s c p1 c p2 ++ () ? ? =t s < () ? v a c f ? v a1 +c p1 c p2 +c s + () ? =
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 70 figure 17. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 12 between the ideal and real sampled voltage on c s : eqn. 12 from this formula, in the worst case (when v a is maximum, that is fo r instance 5v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 13 3.14.2 adc electrical characteristics f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? >
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 71 table 32. adc electrical characteristics symbol parameter conditions 1 value 2 unit min typ max v ssa sr voltage on vssa (adc reference) pin with respect to ground (v ss ) 3 -0.1 0.1 v v dda sr voltage on vdda pin (adc reference) with respect to ground (v ss ) v dd -0.1 v dd +0.1 v v ainx sr analog input voltage 4 v ssa -0.1 v dda +0.1 v f adc sr adc analog frequency 6 32 mhz t adc_pu sr adc power up delay 1.5 s t adc_s cc 5 sample time 6 f adc = 32 mhz, adc_conf_sample_input = 17 0.5 s f adc = 6 mhz, adc_conf_sample_input = 127 21 t adc_c cc 5 conversion time 7 f adc = 32 mhz, adc_conf_comp = 2 0.625 s c s cc 5 adc input sampling capacitance 3 pf c p1 cc 5 adc input pin capacitance 1 3 pf c p2 cc 5 adc input pin capacitance 2 1 pf c p3 cc 5 adc input pin capacitance 3 1 pf r sw1 cc 5 internal resistance of analog source 3 k r sw2 cc 5 internal resistance of analog source 2 k r ad cc 5 internal resistance of analog source 0.1 k i inj sr input current injection current injection on one adc input, different from the converted one -10 10 ma inl cc 5 integral non linearity no overload -1.5 1.5 lsb dnl cc 5 differential non linearity no overload -1.0 1.0 lsb ofs cc 5 offset error after offset cancellation -1.0 1.0 lsb gne cc 5 gain error -1.0 1.0 lsb
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 72 3.15 ac specifications 3.15.1 pad ac specifications tuep cc 5 total unadjusted error for precise channels, input only pins no overload -2 2 lsb overload conditions on adjacent channel lsb tuex cc 5 total unadjusted error for extended channel, no overload -3 3 lsb overload conditions on adjacent channel lsb 1 v dda = 3.3 v 10% / 5.0 v 10%, t a = -40 to +105 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 analog and digital v ss must be common (to be tied together externally). 4 v ainx may exceed v ssa and v dda limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff 5 guaranteed by design 6 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capaci tance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 7 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. table 33. pad ac specifications (5.0 v, ipp_hve=1) 1 num pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew 3 (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow 1.5-306 -50- - 40.04- 2 25 1.5 - 30 9 - 100 - - 2 0.04 - 2 50 1.5 - 30 12 - 125 - - 2 0.04 - 2 100 1.5 - 30 16 - 150 - - 2 0.04 - 2 200 2 medium 1 - 15 3 - 10 - - 40 2.5 - 7 25 1 - 15 5 - 20 - - 20 2.5 - 7 50 1 - 15 9 - 40 - - 13 2.5 - 8 100 1 - 15 12 - 70 - - 7 2.5 - 8 200 table 32. adc electrical characteristics (continued) symbol parameter conditions 1 value 2 unit min typ max
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 73 3 fast 1-61-4- -10018-55 25 1 - 6 1.5 - 6 - - 80 18 - 55 50 1 - 6 3 -12- -4018-55 100 1 - 6 5 -16- -2518-55 200 4 symmetric 1 - 5 1 - 4 - - 50 10 - 25 25 5 pull up/down (5.5 v max) -----5000------ 50 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition 2 slope at rising/falling edge 3 data based on characterization results, not tested in production table 34. pad ac specifications (3.3 v, ipp_hve=0) 1 1 propagation delay from v dd /2 of internal signal to pchannel/nchannel on condition num pad tswitchon 1 (ns) rise/fall 2 (ns) 2 slope at rising/falling edge frequency (mhz) current slew 3 (ma/ns) 3 data based on characterization results, not tested in production load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 - 40 4 - 40 - - 4 0.01 - 2 25 3 - 40 6 - 50 - - 2 0.01 - 2 50 3 - 40 10 - 75 - - 2 0.01 - 2 100 3 - 40 14 - 100 - - 2 0.01 - 2 200 2 medium 1 -152 -12- -402.5- 7 25 1 - 15 4 - 25 - - 20 2.5 - 7 50 1 - 15 8 - 40 - - 13 2.5 - 7 100 1 - 15 14 - 70 - - 7 2.5 - 7 200 3 fast 1 - 6 1 - 4 - -723 -40 25 1-61.5-7- -553-40 50 1 - 6 3 -12- -403 -40 100 1 - 6 5 -18- -253 -40 200 4symmetric1-62-6- -503-25 25 5 pull up/down (3.6 v max) -----7500------ 50 table 33. pad ac specifications (5.0 v, ipp_hve=1) 1 (continued) num pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew 3 (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 74 figure 18. pad output delay 3.16 ac timing 3.16.1 ieee 1149.1 interface timing table 35. jtag interface timing 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at v dd = 3.0 v to 5.5 v, t a = -40 to 105 c, and cl = 50 pf with src = 0b11. num symbol characteristic min max unit 1t jcyc cc 2 tck cycle time 100 ? ns 2t jdc cc 2 tck clock pulse width (measured at v dd /2) 40 60 ns 3t tckrise cc 2 tck rise and fall times (40% ? 70%) ? 3 ns 4t tmss, t tdis cc 2 tms, tdi data setup time 5 ? ns 5t tmsh, t tdih cc 2 tms, tdi data hold time 25 ? ns 6t tdov cc 2 tck low to tdo data valid ? 35 ns 7t tdoi cc 2 tck low to tdo data invalid 0 ? ns 8t tdohz cc 2 tck low to tdo high impedance ? 30 ns 9t bsdv cc 2 tck falling edge to output valid ? 35 ns 10 t bsdvz cc 2 tck falling edge to output valid out of high impedance ?50ns 11 t bsdhz cc 2 tck falling edge to output high impedance ? 50 ns 12 t bsdst cc 2 boundary scan input valid to tck rising edge 50 ? ns 13 t bsdht cc 2 tck rising edge to boundary scan input invalid 50 ? ns v dd /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 75 figure 19. jtag test clock input timing figure 20. jtag test access port timing 2 parameter values guaranteed by design. tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 76 figure 21. jtag boundary scan timing tck output signals input signals output signals 9 10 11 12 13
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 77 3.16.2 nexus debug interface figure 22. nexus clock timing figure 23. nexus output timing table 36. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 3.0 v to 5.5v, t a = -40 to 105 c, and cl = 50 pf (cl=30 pf on mcko), with src = 0b11. num symbol characteristic min max unit 1t mcyc cc 2 2 parameter values guaranteed by design. mcko cycle time 22 ? ns 2t mdc cc 2 mcko duty cycle 40 60 % 3t mdov cc 2 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until next mcko low cycle. ?2 14 ns 4t mseov cc 2 mcko low to mseo data valid 3 ?2 14 ns 5t evtov cc 2 mcko low to evto data valid 3 ?2 14 ns 6t evtipw cc 2 evti pulse width 4 ? t tcyc 7t evtopw cc 2 evto pulse width 1 ? t mcyc 8t tcyc cc 2 tck cycle time 4 4 the system clock frequency needs to be th ree times faster that the tck frequency. 100 ? ns 9t tdc cc 2 tck duty cycle 40 60 % 10 t ntdis, t ntmss cc 2 tdi, tms data setup time 25 ? ns 11 t ntdih, t ntmsh cc 2 tdi, tms data hold time 5 ? ns 12 t jov cc 2 tck low to tdo data valid 0 35 ns 1 2 4 5 mcko mdo mseo evto output data valid 3
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 78 figure 24. nexus tck timing figure 25. nexus tdi, tms, tdo timing 3.16.3 interface to tft lcd panels figure 26 depicts the lcd interface timing for a ge neric active matrix color tft panel. in this figure signals are shown with positive polarity. th e sequence of events for activ e matrix interface timing is: ? dcu_clk latches data into the panel on its positive edge (when positive polarity is selected). in active mode, dcu_clk runs continuously. this signal frequency co uld be from 5 to 66 mhz depending on the panel type. tck 8 9 9 tdo 10 11 tms, tdi 12 tck
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 79 ? dcu_hsync causes the panel to start a new line. it always encompasses at least one pclk pulse. ? dcu_vsync causes the panel to start a new frame. it always encompasses at least one hsync pulse. ? dcu_de acts like an output enable signal to the lcd panel. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. figure 26. tft lcd interfacetiming overview 1 3.16.3.1 interface to tft lcd panels?pixel level timings figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. all parameters shown in the diagram are programmable. this timing diagra m corresponds to positive polarity of the dcu_clk signal (meaning the data and sync signals cha nge on the rising edge) and active-high polarity of the dcu_hsync, dcu_vsync and dcu_de signals. the user can select the polarity of the dcu_hsync and dcu_vsync signals via the syn_pol register, whether active-high or active- low. the default is active-high. the dcu_de signal is always active-high. pixel clock inversion and a flexible programmable pixel cloc k delay are also supported. they are programmed via the dcu clock confide register (dccr) in the system clock module. the delta_x and delta_y parameters are programmed vi a the disp_size register. the pw_h, bp_h and fp_h parameters are programmed via the hsyn para register. the pw_v, bp_v and fp_v parameters are programmed via the vsyn_para register. 1. in figure 26 , the ?dcu_ld[23:0]? signal is an aggregation of the dcu?s rgb signals?dc u_r[0:7], dcu_ g[0:7] and dcu_b[0:7]. table 37. lcd interface timing parameters?horizontal and vertical num symbol characteristic value unit 1t pcp cc 1 display pixel clock period 31.25 ns 2t pwh cc 1 hsync pulse width pw_h * t pcp ns 3t bph cc 1 hsync back porch width bp_h * t pcp ns 4t fph cc 1 hsync front porch width fp_h * t pcp ns 5t sw cc 1 screen width delta_x * t pcp ns line 1 line 2 line 3 line 4 line n-1 line n dcu_vsync dcu_hsync dcu_hsync dcu_de dcu_clk dcu_ld[23:0] 2 1 3 m-1 m
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 80 figure 27. horizontal sync timing figure 28. vertical sync pulse 6t hsp cc 1 hsync (line) period (pw_h + bp_h + fp_h + delta_x ) * t pcp ns 7t pwv cc 1 vsync pulse width pwv * t hsp ns 8t bpv cc 1 vsync back porch width bp_v * t hsp ns t fpv cc 1 vsync front porch width fp_v * t hsp ns t sh cc 1 screen height delta_y * t hsp ns t vsp cc 1 vsync (frame) period (pw_v + bp_v + fp_v + delta_y ) * t hsp ns 1 parameter values guaranteed by design. table 37. lcd interface timing parameters?horizontal and vertical (continued) num symbol characteristic value unit start of line dcu_clk dcu_ld[23:0] dcu_hsync dcu_de t pwh t bph t hsp t sw t pcp t fph 1 2 3 delta_x invalid data invalid data start of frame dcu_hsync dcu_ld[23:0] dcu_hsync dcu_de t pwv t bpv t vsp t hcp t fpv 1 2 3 delta_y invalid data invalid data (line data) t sh
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 81 3.16.3.2 interface to tft lcd panels?access level figure 29. lcd interface timing parameters?access level 3.16.4 external interrupt (irq) and no n-maskable interrupt (nmi) timing table 38. lcd interface timing parameters 1,2,3,4 ?access level 1 the characteristics in this table are based on the assumpti on that data is output at +ve edge and displays latch data on -ve edge 2 intra bit skew is less than 2 ns 3 load cl = 50 pf for frequency up to 20 mhz 4 load cl = 25 pf for display freq from 20 to 32 mhz num symbol characteristic min. value typical value max. value unit 1t ckp cc 5 5 parameter values guaranteed by design. pdi clock period 31.25 ? ns 2t chd cc 5 duty cycle 40 ? 60 % 3t dsu cc 5 interface data setup time 6 ? ns 4t dhd cc 5 pdi interface data access hold time 1 ? ns 5t csu cc 5 pdi interface control signal setup time 3 ? ns 6t chd cc 5 pdi interface control signal hold time 1 ? ns 7cc 5 tft interface data valid after pixel clock ? 6 ns 8cc 5 tft interface hsync valid after pixel clock ? 5 ns 9cc 5 tft interface vsync valid after pixel clock ? 5.5 ns 10 cc 5 tft interface de valid after pixel clock ? 5.6 ns 11 cc 5 tft interface hold time for data and control bits 2? ns 12 cc 5 relative skew between the data bits ? 3.7 ns dcu_hsync dcu_vsync dcu_de dcu_clk dcu_ld[23:0] t ckh t ckl t chd t csu t dhd t dsu
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 82 figure 30. irq and nmi timing 3.16.5 enhanced modular i/o subsystem (emios) timing 3.16.6 flexcan timing the can functions are available as tx pins at normal io pads and as rx pins at the always on domain. there is no filter for the wakeup dominant pulse . any high-to-low edge can cause wakeup if configured. table 39. irq and nmi timing num symbol characteristic min. value max. value unit 1t ipwl cc 1 1 parameter values guaranteed by design. irq/nmi pulse width low 200 ? ns 2t ipwh cc 1 irq/nmi pulse width high 200 ? ns 3t icyc cc 1 irq/nmi edge to edge time 2 2 applies when irq/nmi pins are configured for rising edge or falling edge events, but not both. 400 ? ns table 40. emios timing 1 1 emios timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = -40 to 105 c, and cl = 50 pf with src = 0b00 num symbol characteristic min. value 2 2 there is no limitation on the peripheral for setting the minimu m pulse width, the actual width is restricted by the pad delays. refer to the pad specification section for the details. max. value unit 1t mipw cc 3 3 parameter values guaranteed by design. emios input pulse width 4 ? t cyc 2t mopw cc 3 emios output pulse width 1 ? t cyc table 41. flexcan timing 1 num symbol characteristic min. value max. value unit 1t canov cc 2 ctnx output valid after cl kout rising edge (output delay) ? 22.48 ns 2t cansu cc 2 cnrx input valid to clkout rising edge (setup time) ? 12.46 ns 1,2 3 1,2
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 83 3.16.7 deserial serial peripheral interface (dspi) 1 flexcan timing specified at f sys = 64 mhz, v dd12 = 1.14 v to 1.32 v, vdde_x = 3.0 v to 5.5 v, t a = -40 to 105 c, and cl = 50 pf with src = 0b00. 2 parameter values guaranteed by design. table 42. dspi timing 1 1 dspi timing specified at vdde_x = 3.0 v to 5.5v, t a = -40 to 105 c, and cl = 50 pf with src = 0b11. num symbol characteristic min max unit 1t sck cc 2 2 parameter values guaranteed by design. sck cycle time 3,4 3 the minimum sck cycle time rest ricts the baud rate selectio n for given system clock rate. 4 the actual minimum sck cycle time is limited by pad performance. 60 ? ns 2t csc cc 2 pcs to sck delay 5 5 the maximum value is programmable in dspi_ctarx [pssck] and dspi_ctarx[cssck], program pssck=2 & cssck = 2 -?ns 3t asc cc 2 after sck delay 6 6 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc] 20 ? ns 4t sdc cc 2 sck duty cycle t sck /2 ?2ns t sck/2 + 2ns ns 5t a cc 2 slave access time (pcsx active to sout driven) ? 25 ns 6t dis cc 2 slave sout disable time (pcsx inactive to sout high-z or invalid) ? 25 ns 7t sui cc 2 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) 7 this delay value is corresponding to smpl_pt=00b which is bit field 9 and 8 of dspi_mcr register. 35 5 5 35 ? ? ? ? ns ns ns ns 8t hi cc 2 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) ?4 10 26 ?4 ? ? ? ? ns ns ns ns 9t suo cc 2 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha=0) master (mtfe = 1, cpha=1) ? ? ? ? 15 35 30 15 ns ns ns ns 10 t ho cc 2 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) ?15 5.5 0 ?15 ? ? ? ? ns ns ns ns
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 84 figure 31. dspi classic spi timing ? master, cpha = 0 figure 32. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 7 10 1 9 8 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 10 9 8 last data data first data sck output sck output pcsx 7 (cpol=0) (cpol=1)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 85 figure 33. dspi classic spi timing ? slave, cpha = 0 figure 34. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol=0) (cpol=1)
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 86 figure 35. dspi modified transfer format timing ? master, cpha = 0 figure 36. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 8 4 7 10 9 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 8 7 10 9 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 87 figure 37. dspi modified transfer format timing ? slave, cpha = 0 figure 38. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout pcsx 4 5 6 7 9 8 sck input first data last data sck input 2 (cpol=0) (cpol=1) 10 5 6 7 10 9 8 last data last data sin sout pcsx first data first data data data sck input sck input (cpol=0) (cpol=1)
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 88 3.16.8 i 2 c timing table 43. i 2 c input timing specifications?scl and sda num symbol characteristic min. value max. value unit 1?cc 1 1 parameter values guaranteed by design. start condition hold time 2 ? ip-bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device 2?cc 1 clock low time 8 ? ip-bus cycle 2 4?cc 1 data hold time 0.0 ? ns 6?cc 1 clock high time 4 ? ip-bus cycle 2 7?cc 1 data setup time 0.0 ? ns 8?cc 1 start condition setup time (for repeated start condition only) 2 ? ip-bus cycle 2 9?cc 1 stop condition setup time 2 ? ip-bus cycle 2 table 44. i 2 c output timing specifications?scl and sda num symbol characteristic min. value max. value unit 1 1 1 programming ibfd ( i 2 c bus frequency divider ) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed in ifdr. ?cc 2 2 parameter values guaranteed by design. start condition hold time 6 ? ip-bus cycle 3 3 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device 2 1 ?cc 2 clock low time 10 ? ip-bus cycle 2 3 4 4 because scl and sda are open-drain-type outputs, which th e processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pull-up resistor values. ?cc 2 scl/sda rise time ? 99.6 ns 4 1 ?cc 2 data hold time 7 ? ip-bus cycle 2 5 1 ?cc 2 scl/sda fall time ? 99.5 ns 6 1 ?cc 2 clock high time 10 ? ip-bus cycle 2 7 1 ?cc 2 data setup time 2 ? ip-bus cycle 2 8 1 ?cc 2 start condition setup time (for repeated start condition only) 20 ? ip-bus cycle 2 9 1 ?cc 2 stop condition setup time 10 ? ip-bus cycle 2
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 89 figure 39. i 2 c input/output timing 3.16.9 mechanical outline drawings 3.17 144 lqfp scl sda 1 2 3 4 5 6 7 8 9
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 90 figure 40. lqfp144 mechanical drawing (part 1 of 3)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 91 figure 41. lqfp144 mechanical drawing (part 2 of 3)
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 92 figure 42. lqfp144 mechanical drawing (part 3 of 3)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 93 3.18 176 lqfp figure 43. lqfp176 mechanical drawing (part 1 of 3)
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 94 figure 44. lqfp176 mechanical drawing (part 2 of 3)
electrical characteristics mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 95 figure 45. lqfp176 mechanical drawing (part 3 of 3)
mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice ordering information freescale semiconductor 96 4 ordering information table 45 shows the orderable part numbers for the MPC5606S series. figure 46. commercial product code structure 1 208 mapbga available only as de velopment package for nexus2+ table 45. orderable part number summary part number flash/sram package speed (mhz) mpc5602semlq 256 kb/24 kb 144 lqfp 64 mpc5604semlq 512 kb/48 kb 144 lqfp 64 mpc5604semlq 512 kb/48 kb 144 lqfp 64 MPC5606Semlq 1 mb/48 kb 1 1 device also includes 160 kb of graphics sram. 144 lqfp 64 MPC5606Semlu 1 mb/48 kb 1 176 lqfp 64 qualification status powerpc core automotive platform core version flash size (core dependent) product optional fields mpc56 semll example code: 04 temperature spec. package code qualification status m = mc status s = auto qualified p = pc status automotive platform 56 = ppc in 90nm 57 = ppc in 65nm flash size (z0 core) 2 = 256 kb 4 = 512 kb 6 = 1024 kb product b = body c = gateway r = tape & reel (blank if tray) r temperature spec. c = ?40 c to 85c v = ?40 c to 105c m = ?40 c to 125c package code lq = 144 lqfp lu = 176 lqfp mg = 208 mapbga 1
ordering information mpc560xs microcontroller data sheet data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 97
document number: MPC5606S rev. 1 10/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2008. all rights reserved. preliminary?subject to change without notice

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